Datasheet

Processor Integrated I/O (IIO) Configuration Registers
144 Datasheet, Volume 2
3.5.2.4 GLBCMD[0:1]—Global Command Register
Register: GLBCMD[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 18h, 1018h
Bit Attr Default Description
31 RV 0 Reserved
30 RW 0
Set Root Table Pointer
Software sets this field to set/update the root-entry table pointer used by
hardware. The root-entry table pointer is specified through the Root-entry Table
Address register.
Hardware reports the status of the root table pointer set operation through the
RTPS field in the Global Status register.
Clearing this bit has no effect.
29 RO 0 Reserved (N/A to IIO)
28 RO 0 Reserved (N/A to IIO)
27 RO 0 Reserved (N/A to IIO)
26 RW 0
Queued Invalidation Enable
Software writes to this field to enable queued invalidations.
0 = Disable queued invalidations. In this case, invalidations must be performed
through the Context Command and IOTLB Invalidation registers.
1 = Enable use of queued invalidations. Once enabled, all invalidations must be
submitted through the invalidation queue and the invalidation registers
cannot be used without going through an IIO Reset. The invalidation queue
address register must be initialized before enabling queued invalidations. Also
software must make sure that all invalidations submitted prior using the
register interface are all completed before enabling the queued invalidation
interface.
25 RW 0
Interrupt Remapping Enable:
0 = Disable Interrupt Remapping Hardware
1 = Enable Interrupt Remapping Hardware
Hardware reports the status of the interrupt-remap enable operation through the
IRES field in the Global Status register.
Before enabling (or re-enabling) Interrupt-remapping hardware through this field,
software must:
• Setup the interrupt-remapping structures in memory
• Set the Interrupt Remap table pointer in hardware (through SIRTP field).
• Perform global invalidation of IOTLB
24 RV 0 Reserved
23 RV 0 Reserved
22:0 RV 0 Reserved