Datasheet

Datasheet, Volume 2 143
Processor Integrated I/O (IIO) Configuration Registers
3.5.2.3 EXT_VTD_CAP[0:1]—Extended Intel
®
VT-d Capability Register
Register: EXT_VTD_CAP[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 10h, 1010h
Bit Attr Default Description
63:24 RV 0 Reserved
23:20 RO Fh
Max Handle Mask Value
IIO supports all 16 bits of handle being masked.
Note: IIO always performs global interrupt entry invalidation on any interrupt
cache invalidation command and h/w never really looks at the mask value.
19:18 RV 0 Reserved
17:8 RO 20h
Invalidation Unit Offset
IIO has the invalidation registers at offset 200h
7RWO
0 (offset
1010h)
1 (offset
10h)
0 = Hardware does not support 1-setting of the SNP field in the page-table
entries.
1 = Hardware supports the 1-setting of the SNP field in the page-table entries.
IIO supports snoop override only for the non-isochronous Intel VT-d engine.
6RV 1Reserved
5RO 1
Caching hints
IIO supports caching hints
4RO 0Reserved
3RWO 1
Interrupt Remapping Support
IIO supports this
2RV
0 (offset
1010h)
1 (offset
10h)
Reserved
1RWO 1
Queued Invalidation Support
IIO supports this.
0RWO 0
Coherency Support
BIOS can write to this bit to indicate to hardware to either snoop or not-snoop
the DMA/Interrupt table structures in memory (root/context/pd/pt/irt). Note
that this bit is expected to be always set to 0 for the Isochronous Intel
VT-d
engine.