Datasheet

Processor Integrated I/O (IIO) Configuration Registers
142 Datasheet, Volume 2
3.5.2.2 VTD_CAP[0:1]—Intel
®
VT-d Chipset Capabilities Register
(Sheet 1 of 2)
Register: VTD_CAP[0:1]
Addr: MMIO
BAR: VTBAR
Offset: 08h, 1008h
Bit Attr Default Description
63:56 RV 0 Reserved
55:54 RO 11b Reserved
53:48 RO 09h
Max Address Mask Value (MAMV)
IIO supports MAMV value of 9h.
47:40 RO
Off:def
7h (non-
Isoch)
0h (Isoch)
Number of Fault Recording Registers
IIO supports 8 fault recording registers for non-isochronous Intel VT-d engine,
and 1 fault recording register for isochronous Intel VT-d engine.
39 RO 1
Page Selective Invalidation
Supported in IIO (Integrated I/O)
38 RV 0 Reserved
37:34 RO 0h Reserved
33:24 RO 10h
Fault Recording Register Offset
Fault registers are at offset 100h
23 RWO
Off:def
08h: 0
else: 1
Isoch
This bit is set to 1 for isochronous Intel VT-d engine and 0 for the non-
isochronous engine.
22 RV 1 Reserved
21:16 RO
Off:def
08h: 2Fh
else: 26h
MGAW
For non-isochronous Intel VT-d engine, this field is set based on the setting of
the Non-Isoch GPA_LIMIT field in the VTGENCTRL register. Similarly for isoch
Intel VT-d engine, this field is set by the Isoch GPA_LIMIT field of the
VTGENCTRL register.
15 RV 0h Reserved
14:13 RO 0h Reserved
12:8 RO
Off:def
08h: 4h
else: 2h
SAGAW
IIO supports 3 level walks on the Isochronous Intel
VT-d engine and 4 level
walks on the non-Isochronous Intel
VT-d engine.
7RO 0
TCM
IIO does not cache invalid pages.
6RO 1
PHMR Support
IIO supports protected high memory range.
5RO 1
PLMR Support
IIO supports protected low memory range.
4RO 0Reserved
3RO 0
Advanced Fault Logging
IIO does not support advanced fault logging.
2:0 RO 010b
Number of Domains Supported
IIO supports 256 domains with 8-bit domain ID