Datasheet

14 Datasheet, Volume 2
4-13 Device 4, Function 3 — Integrated Memory Controller Channel 0
Thermal Control Registers.................................................................................196
4-14 Device 5, Function 0 — Integrated Memory Controller Channel 1
Control Registers.............................................................................................197
4-15 Device 5, Function 1 — Integrated Memory Controller Channel 1
Address Registers............................................................................................198
4-16 Device 5, Function 2 — Integrated Memory Controller Channel 1
Rank Registers................................................................................................199
4-17 Device 5, Function 3 — Integrated Memory Controller Channel 1
Thermal Control Registers.................................................................................200
4-18 Padscan Accessible Parameters..........................................................................229
4-19 Scan Chains....................................................................................................229
4-20 Halt and Mask Bit Usage...................................................................................230
4-21 Padscan Registers............................................................................................230
5-1 Transaction Address Ranges – Compatible, High, and TSEG...................................287
5-2 SMM Space Table.............................................................................................288
5-3 SMM Control Table...........................................................................................289
5-4 Outbound Target Decoder Entries ......................................................................293
5-5 Decoding of Outbound Memory Requests from Intel
®
QuickPath Interconnect
(from processor or remote Peer-to-Peer) ............................................................293
5-6 Decoding of Outbound Configuration Requests (from Processor or Peer-to-
Peer) from Intel
®
QuickPath Interconnect and Decoding of Outbound
Peer-to-Peer Completions from Intel QuickPath Interconnect .................................294
5-7 Subtractive Decoding of Outbound I/O Requests from Intel
®
QuickPath Interconnect 294
5-8 Inbound Memory Address Decoding....................................................................296
5-9 Inbound I/O Address Decoding..........................................................................298
5-10 Inbound Configuration Request Decoding............................................................299