Datasheet

Processor Integrated I/O (IIO) Configuration Registers
138 Datasheet, Volume 2
3.5.1 Intel
®
VT-d Configuration Register Space (MMIO)
Table 3-13. Intel
®
VT-d Memory Mapped Registers — 00h–FFh, 1000h–10FFh
VER_REG 00h
INV_QUEUE_HEAD_REG
80h
04h 84h
CAP_REG
08h
INV_QUEUE_TAIL_REG
88h
0Ch 8Ch
EXTCAP_REG
10h
INV_QUEUE_ADD_REG
90h
14h 94h
GLBCMD_REG 18h
98h
GLBSTS_REG 1Ch INV_COMP_STATUS_REG 9Ch
ROOTENTRYADDR_REG
20h INV_COMP_EVT_CTL_REG A0h
24h INV_COMP_EVT_DATA_REG A4h
CTXCMD_REG
28h INV_COMP_EVT_ADDR_REG A8h
2Ch INV_COMP_EVT_UPRADDR_REG ACh
30h B0h
FLTSTS_REG 34h
B4h
FLTEVTCTRL_REG 38h
INTR_REMAP_TABLE_BASE_REG
B8h
FLTEVTDATA_REG 3Ch BCh
FLTEVTADDR_REG 40h
C0h
FLTEVTUPRADDR_REG 44h
C4h
48h C8h
4Ch CCh
50h D0h
54h D4h
58h D8h
5Ch DCh
60h E0h
PMEN_REG 64h
E4h
PROT_LOW_BASE_REG 68h
E8h
PROT_LOW_MEM_LIMIT_REG 6Ch
ECh
PROT_HIGH_MEM_BASE_REG
70h
F0h
74h
F4h
PROT_HIGH_MEM_LIMIT_REG
78h
F8h
7Ch
FCh