Datasheet

Datasheet, Volume 2 131
Processor Integrated I/O (IIO) Configuration Registers
3.4.5.11 CWR[16:17]—Conditional Write Registers 16-17
3.4.5.12 CWR[18:23]—Conditional Write Registers 18-23
3.4.5.13 IR[0:3]—Increment Registers 0-3
Register: CWR[16:17]
Device: 8
Function: 1
Offset: 18h-124h by 4
Bit Attr Default Description
31:0 RWLB 0h
Conditional Write
These registers are physically mapped to scratch pad registers. A read from
CWR[n] reads SR[n]. A write to CWR[n] writes SR[n] if SR[n][0] = 0 before the
write, and has no effect otherwise. The registers provide firmware with
synchronization variables (semaphores) that are overloaded onto the same
physical registers as SR.
Register: CWR[18:23]
Device: 8
Function: 1
Offset: 128h-13Ch by 4
Bit Attr Default Description
31:0 RW 0h
Conditional Write
These registers are physically mapped to scratch pad registers. A read from
CWR[n] reads SR[n]. A write to CWR[n] writes SR[n] if SR[n][0] = 0 before the
write, and has no effect otherwise. The registers provide firmware with
synchronization variables (semaphores) that are overloaded onto the same
physical registers as SR.
Register: IR[0:3]
Device: 8
Function: 1
Offset: 140h-14Ch by 4
Bit Attr Default Description
31:0 RWSLB 0h
Increment
These registers are physically mapped to scratch pad registers. A read from IR[n]
reads SR[n] and then increments SR[n]. A write to IR[n] increments SR[n] while
the write data is unused. Increments within SR[n] for reads and writes roll over to
zero. The read or write and the increment side effect are atomic with respect to
other accesses. The registers provide firmware with synchronization variables
(semaphores) that are overloaded onto the same physical registers as SR.