Datasheet
Datasheet, Volume 2 13
Figures
2-1 Memory Map to PCI Express* Device Configuration Space.......................................22
2-2 Processor Configuration Cycle Flowchart...............................................................23
3-1 DMI Port (Device 0) and PCI Express* Root Ports Type 1 Configuration Space ...........29
3-2 Base Address of Intel
®
VT-d Remap Engines....................................................... 137
4-1 Padscan Accessibility Mechanism....................................................................... 230
5-1 System address Map........................................................................................ 277
5-2 VGA/SMM and Legacy C/D/E/F Regions .............................................................. 279
5-3 Pre-allocated Memory Example for 64 MB DRAM, 1 MB VGA, 1 MB GTT Stolen
and 1 MB TSEG............................................................................................... 281
Tables
3-1 Functions Handled by the Processor Integrated I/O (IIO)........................................28
3-2 Device 0 (DMI) Configuration Map .......................................................................31
3-3 Device 0 (DMI) Extended Configuration Map .........................................................32
3-4 Device 3,5 PCI Express* Registers Legacy Configuration Map..................................33
3-5 Device 3,5 PCI Express* Registers Extended Configuration Map...............................34
3-6 DMI RCRB Registers ..........................................................................................84
3-7 Core Registers (Device 8, Function 0) — Offset 000h–0FFh ..................................... 92
3-8 Core Registers (Device 8, Function 0) — Offset 100h–1FFh ..................................... 93
3-9 Core Registers (Device 8, Function 1) — Semaphore and ScratchPad
Registers (Sheet 1 of 2).....................................................................................94
3-10 Core Registers (Device 8, Function 1) — Semaphore and ScratchPad
Registers (Sheet 2 of 2).....................................................................................95
3-11 Core Registers (Device 8, Function 2) — System Control/Status Registers.................96
3-12 Core Registers (Device 8, Function 3) — Miscellaneous Registers.............................97
3-13 Intel
®
VT-d Memory Mapped Registers — 00h–FFh, 1000h–10FFh ......................... 138
3-14 Intel
®
VT-d Memory Mapped Registers — 100h–1FFh, 1100h–11FFh...................... 139
3-15 Intel
®
Trusted Execution Technology Registers.................................................... 157
3-16 Intel
®
Trusted Execution Technology Registers, cont’d ......................................... 158
3-17 Intel
®
Trusted Execution Technology Registers, cont’d ......................................... 159
3-18 Intel
®
Trusted Execution Technology Registers, cont’d ......................................... 160
3-19 Intel
®
Trusted Execution Technology Registers, cont’d ......................................... 161
3-20 Intel
®
QuickPath Interconnect Physical/Link Map Port 0 (Device 16)....................... 176
3-21 CSR Intel
®
QuickPath Interconnect Routing Layer, Protocol (Device 16, Function 1). 180
4-1 Functions Specifically Handled by the Processor................................................... 184
4-2 Device 0, Function 0 — Generic Non-core Registers ............................................. 185
4-3 Device 0, Function 1 — System Address Decoder Registers................................... 186
4-4 Device 2, Function 0 — Intel
®
QuickPath Interconnect Link 0 Registers .................. 187
4-5 Device 2, Function 1 — Intel
®
QuickPath Interconnect Physical 0 Registers............. 188
4-6 Device 3, Function 0 — Integrated Memory Controller Registers ............................ 189
4-7 Device 3, Function 1 — Target Address Decoder Registers .................................... 190
4-8 Device 3, Function 2 — Memory Controller Test Registers ..................................... 191
4-9 Device 3, Function 4 — Integrated Memory Controller Test Registers...................... 192
4-10 Device 4, Function 0 — Integrated Memory Controller Channel 0
Control Registers............................................................................................. 193
4-11 Device 4, Function 1 — Integrated Memory Controller Channel 0
Address Registers............................................................................................ 194
4-12 Device 4, Function 2 — Integrated Memory Controller Channel 0
Rank Registers................................................................................................ 195