Datasheet

Datasheet, Volume 2 127
Processor Integrated I/O (IIO) Configuration Registers
3.4.4.31 VTISOCHCTRL—Intel VT-d Isoch Related Control Register
3.4.4.32 VTGENCTRL2—Intel VT-d General Control 2 Register
Register: VTISOCHCTRL
Device: 8
Function: 0
Offset: 188h
Bit Attr Default Description
31:5 RV 0 Reserved
4:2 RWL 0
Number of Isoch cache entries when Isoch Intel VT-d engine is enabled:
000 = 0 entries
001 = 1 entry
010 = 2 entries
Others = Reserved
1RWL 0
2 entries for isochronous Desc
This field may be locked as RO in Intel
TXT mode
0RWL 1
Steer isochronous to non-isochronous Intel VT-d engine
This field may be locked as RO in Intel
TXT mode
Register: VTGENCTRL2
Device: 8
Function: 0
Offset: 18Ch
Bit Attr Default Description
31:11 RV 0 Reserved
10:7 RWL Fh LRU Timer
6:5 RWL 01
Prefetch Control
This field controls which Intel VT-d reads are to be considered for
prefetch/snarf/reuse in the Intel
QuickPath Interconnect buffers.
00 = Prefetch/snarf/reuse is disabled.
01 = Prefetch/snarf/reuse is enabled for all leaf/non-leaf Intel VT-d page
walk reads.
Others = Reserved
4RV 0Reserved
3RV 0Reserved
2RV 0Reserved
1RV 0Reserved
0RV 0Reserved