Datasheet

Processor Integrated I/O (IIO) Configuration Registers
124 Datasheet, Volume 2
3.4.4.26 GCFGBUS.LIMIT—Global Configuration Bus Number Limit Register
3.4.4.27 MESEGBASE—Intel
®
Management Engine (Intel
®
ME)
Memory Region Base
The MESEGBASE and MESEGMASK registers are used for protecting Intel
®
Management Engine (Intel ME) stolen memory from processor accesses.
3.4.4.28 MESEGMASK—Intel
®
ME Memory Region Mask
Register: GCFGBUS.LIMIT
Device: 8
Function: 0
Offset: 135h
Bit Attr Default Description
7:0 RW FFh
Global Configuration Bus Number Limit
This field corresponds to limit bus number of bus number range allocated
across all IIOs in the partition. An inbound or outbound configuration that
satisfies ‘Global Bus Number Base [7:0] ≤ Bus Number[7:0] ≤ Global Bus
Number Limit [7:0]’ but is outside of the low bus number range is treated as a
remote peer-to-peer transaction over Intel
QuickPath Interconnect link.
This register is programmed once at boot time and does not change after that.
Register: MESEGBASE
Device: 8
Function: 0
Offset: 138h
Bit Attr Default Description
63:36 RV 0 Reserved
35:19 RWL 1FFFFh
Base address of ME SEG
Must be 4-MB aligned. This field is controlled by Bit 10 of MESEGMASK
register.
18:0 RV 0 Reserved
Register: MESEGMASK
Device: 8
Function: 0
Offset: 140H
Bit Attr Default Description
63:36 RV 0 Reserved
35:19 RWL 0
Which bits must match the MESEGBASE in order to be inside the Intel ME
memory region
18:12 RV 0 Reserved
11 RWO 0 Enable for Intel ME memory region
10 RWO 0
Lock for Intel ME memory region base/mask. This bit is only cleared upon a
reset. MESEGMASK and MESEGBASE cannot be changed once this bit is set.
9:0 RV 0 Reserved