Datasheet

Processor Integrated I/O (IIO) Configuration Registers
122 Datasheet, Volume 2
3.4.4.21 GMMIOH.BASE—Global MMIOH Base
3.4.4.22 GMMIOH.LIMIT—Global MMIOH Limit
Register: GMMIOH.BASE
Device: 8
Function: 0
Offset: 128h
Bit Attr Default Description
15:10 RW 00h
Global MMIOH Base Address
This field corresponds to A[31:26] of global MMIOH base. An inbound or
outbound memory address that satisfies ‘global MMIOH base
upper[31:0]::global MMIOH base[15:10] ≤ A[63:26] ≤ global MMIOH limit
upper[31:0]::global MMIOH limit[15:10]’ but is outside of the local MMIOH
range is treated as a remote peer-to-peer transaction over Intel
QuickPath
Interconnect link.
Setting GMMIOH.BASEU::GMMIOH.BASE greater than
GMMIOH.LIMITU::GMMIOH.LIMIT disables global MMIOH peer-to-peer.
This register is programmed once at boot time and does not change after that.
9:0 RO 000h Reserved
Register: GMMIOH.LIMIT
Device: 8
Function: 0
Offset: 12Ah
Bit Attr Default Description
15:10 RW 00h
Global MMIOH Limit Address
This field corresponds to A[31:26] of global MMIOH limit. An inbound or
outbound memory address that satisfies ‘global MMIOH base
upper[31:0]::global MMIOH base[15:10] ≤ A[63:26] ≤ global MMIOH limit
upper[31:0]::global MMIOH limit[15:10]’ but is outside of the local MMIOH
range is treated as a remote peer-to-peer transaction over Intel
QuickPath
Interconnect link.
Setting GMMIOH.BASEU::GMMIOH.BASE greater than
GMMIOH.LIMITU::GMMIOH.LIMIT disables global MMIOH peer-to-peer.
This register is programmed once at boot time and does not change after that.
9:0 RO 000h Reserved