Datasheet

Datasheet, Volume 2 121
Processor Integrated I/O (IIO) Configuration Registers
3.4.4.18 LCFGBUS.LIMIT—Local Configuration Bus Number Limit Register
3.4.4.19 GMMIOL.BASE—Global MMIOL Base
3.4.4.20 GMMIOL.LIMIT—Global MMIOL Limit
Register: LCFGBUS.LIMIT
Device: 8
Function: 0
Offset: 11Dh
Bit Attr Default Description
7:0 RW 00h
Local Configuration Bus Number Limit
This field corresponds to Limit bus number of bus number range allocated to
the hierarchy below the Intel
QuickPath Interconnect link. An inbound or
outbound configuration falls within the local bus number range if ‘Local Bus
Number Base [7:0] Bus Number[7:0] Local Bus Number Limit [7:0]’ and
such transactions are treated as local peer-to-peer transactions that do not
cross an Intel
QuickPath Interconnect link.
Setting LCFGBUS.BASE greater than LCFGBUS.LIMIT disables local peer-to-
peer configuration cycles.
This register is programmed once at boot time and does not change after that.
Register: GMMIOL.BASE
Device: 8
Function: 0
Offset: 124h
Bit Attr Default Description
15:8 RW 00h
Global MMIOL Base Address
This field corresponds to A[31:24] of global MMIOL base. An inbound or
outbound memory address that satisfies ‘global MMIOL base[15:8] A[31:24]
global MMIOL limit[15:8]’ but is outside of the local MMIOL range is treated
as a remote peer memory transaction over Intel
QuickPath Interconnect.
Setting GMMIOL.BASE greater than GMMIOL.LIMIT disables global MMIOL
peer-to-peer.
This register is programmed once at boot time and does not change after that.
7:0 RO 00h Reserved
Register: GMMIOL.LIMIT
Device: 8
Function: 0
Offset: 126h
Bit Attr Default Description
15:8 RW 00h
Global MMIOL Limit Address
This field corresponds to A[31:24] of global MMIOL limit. An inbound or
outbound memory address that satisfies ‘global MMIOL base[15:8] A[31:24]
global MMIOL limit[15:8]’ but is outside of the local MMIOL range is treated
as a remote peer-to-peer transaction over Intel
QuickPath Interconnect link.
Setting GMMIOL.BASE greater than GMMIOL.LIMIT disables global MMIOL
peer-to-peer.
This register is programmed once at boot time and does not change after that.
7:0 RO 00h Reserved