Datasheet

12 Datasheet, Volume 2
5.5 System Management Mode (SMM) .....................................................................287
5.5.1 SMM Space Definition............................................................................287
5.5.2 SMM Space Restrictions.........................................................................288
5.5.3 SMM Space Combinations ......................................................................288
5.5.4 SMM Control Combinations.....................................................................289
5.5.5 SMM Space Decode and Transaction Handling...........................................289
5.5.6 Processor WB Transaction to an Enabled SMM Address Space .....................289
5.5.7 SMM Access Through GTT TLB................................................................289
5.6 Memory Shadowing..........................................................................................290
5.7 IIO Address Map Notes.....................................................................................290
5.7.1 Memory Recovery.................................................................................290
5.7.2 Non-Coherent Address Space .................................................................290
5.8 IIO Address Decoding.......................................................................................291
5.8.1 Outbound Address Decoding...................................................................291
5.8.1.1 General Overview....................................................................291
5.8.1.2 FWH Decoding ........................................................................292
5.8.1.3 Other Outbound Target Decoding ..............................................292
5.8.1.4 Summary of Outbound Target Decoder Entries............................293
5.8.1.5 Summary of Outbound Memory/IO/Configuration Decoding...........293
5.8.2 Inbound Address Decoding.....................................................................295
5.8.2.1 Overview ...............................................................................295
5.8.2.2 Summary of Inbound Address Decoding .....................................296
5.8.3 Intel
®
VT-d Address Map Implications .....................................................300