Datasheet

Processor Integrated I/O (IIO) Configuration Registers
118 Datasheet, Volume 2
3.4.4.10 IIOBUSNO—IIO Internal Bus Number
3.4.4.11 LMMIOL.BASE—Local MMIOL Base
Register: IIOBUSNO
Device: 8
Function: 0
Offset: 10Ah
Bit Attr Default Description
15:9 RV 00h Reserved
8RW 0b
Valid
0 = The IIO claims PCI configuration access to its internal devices
(device/function) defined in Table 3-1, “Functions Handled by the
Processor Integrated I/O (IIO)” with ANY Bus number, regardless of
bits[7:0] of this register.
1 = The IIO (Integrated I/O) claims PCI configuration access to its internal
devices (device/function) defined in Table 3-1, “Functions Handled by the
Processor Integrated I/O (IIO)” with the Bus number defined in bits[7:0]
of this register only.
Since the processor does not support values other than 00 for the bus number,
BIOS should set this bit to 1 to prevent the bus number from changing.
7:0 RW 00h
Internal bus number of IIO (Integrated I/O)
This field is used to compare against the bus # in the Intel
QuickPath
Interconnect configuration tx and decide if the access is to the IIO internal
devices or if it goes out to a bus hierarchy below the IIO’s internal bus.
This register is programmed once at boot time and does not change after that.
For the processor, the default value of 00h is the only valid setting.
Register: LMMIOL.BASE
Device: 8
Function: 0
Offset: 10Ch
Bit Attr Default Description
15:8 RW 00h
Local MMIOL Base Address
This field corresponds to A[31:24] of MMIOL base address. An inbound or
outbound memory address that satisfies ‘local MMIOL base[15:8] ≤ A[31:24] ≤
local MMIOL limit[15:8]’ is treated as a local peer-to-peer transaction that
does not cross an Intel
QuickPath Interconnect link.
Setting LMMIOL.BASE greater than LMMIOL.LIMIT disables local MMIOL peer-
to-peer.
This register is programmed once at boot time and does not change after that.
7:0 RO 0h Reserved