Datasheet

Datasheet, Volume 2 117
Processor Integrated I/O (IIO) Configuration Registers
3.4.4.9 DEVHIDE2—Device Hide 2 Register
This register provides a method to hide the PCI configuration space of devices inside
IIO, from the host initiated configuration accesses. This register does not impact JTAG
initiated accesses to the corresponding device’s configuration space.
When set (for each device), all PCI configuration accesses from Intel
QuickPath
Interconnect targeting the corresponding device’s configuration space inside the
Integrated I/O (IIO) are master aborted. When clear, configuration accesses targeting
the device’s configuration space are allowed.
Note: If software hides Function 0 in Device 8, it needs to hide all functions within that device
to comply with PCI rules.
Register: DEVHIDE2
Device: 8
Function: 0
Offset: F8h
Bit Attr Default Description
31:7 RV 0000000h Reserved
6RV 0bReserved
5RWLB 0b
Hide_Dev8_Fun2
When set, hide Device 8/Function 2.
1. This bit has no effect on JTAG initiated accesses to corresponding
device’s configuration space.
2. This bit has no impact on memory transactions targeting the device.
4RWLB 0b
Hide_Dev8_Fun1
When set, hide Device 8/Function 1.
1. This bit has no effect on JTAG initiated accesses to corresponding
device’s configuration space.
2. This bit has no impact on memory transactions targeting the device.
3RWLB 0b
Hide_Dev8_Fun0
When set, hide Device 8/Function 0.
1. This bit has no effect on JTAG initiated accesses to corresponding
device’s configuration space.
2. This bit has no impact on memory transactions targeting the device.
Note: If Dev8_Fun0 is hidden, then other functions within this device should
also be hidden to comply with PCI rules.
2:0 RV 0h Reserved