Datasheet

Processor Integrated I/O (IIO) Configuration Registers

116 Datasheet, Volume 2

3RWL 0

Hide_Dev3

When set, hide Device 3

1. This bit has no impact on any configuration transactions that

target the secondary side of a device that is a PCI-to-PCI bridge.

2. This bit has no effect on JTAG initiated accesses to corresponding

device’s configuration space.

3. This bit has no impact on memory transactions targeting the

device or memory transactions forwarded through the device.

4. This bit has no impact on IO transactions forwarded through the

device to the PCI Express/DMI link.

5. This bit has no impact on messages forwarded to/through the

device (for example, messages forwarded through a PCI-to-PCI

bridge to PCI Express link)

2:1 RV 0 Reserved

0RWL 0

Hide_Dev0

When set, hide Device 0

1. This bit has no impact on any configuration transactions that

target the secondary side of the PCI-to-PCI bridge

2. This bit has no effect on JTAG initiated accesses to corresponding

device configuration space

3. This bit has no impact on memory transactions forwarded

through the device (for example, memory transactions forwarded

through the Device 0 PCI-to-PCI bridge, to the PCI Express link)

4. This bit has no impact on IO transactions forwarded through the

device to the PCI Express/DMI link.

5. This bit has no impact on messages forwarded to/through the

device (for example, messages forwarded through a PCI-to-PCI

bridge to PCI Express link)

(Sheet 3 of 3)

Device: 8

Function: 0

Offset: F0h

Bit Attr Default Description