Datasheet
Datasheet, Volume 2 115
Processor Integrated I/O (IIO) Configuration Registers
26 RWL 0
Hide_Dev16_Fun0
When set, hide Device #16/Function #0
When set, all PCI configuration accesses from Intel QuickPath
Interconnect targeting the corresponding device’s configuration space
inside IIO are master aborted. When clear, configuration accesses
targeting the device’s configuration space are allowed.
This bit has no effect on smbus and jtag initiated accesses to
corresponding device’s configuration space.
The lock bit is lock1 (“TXTLOCK: TXT Lock Register”)
25:20 RV 00h Reserved
19:12 RV 0 Reserved
12 RWLB 0
Hide_Dev8_Fun3
When set, hide Device 8/Function 3
11:8 RV 0 Reserved
7RV 0Reserved
6RWLB 0
Hide_Dev6
When set, hide Device #6
1. This bit has no impact on any configuration transactions that
target the secondary side of a device that is a PCI-to-PCI bridge.
2. This bit has no effect on JTAG initiated accesses to corresponding
device’s configuration space.
3. This bit has no impact on memory transactions targeting the
device or memory transactions forwarded through the device.
4. This bit has no impact on IO transactions forwarded through the
device to the PCI Express/DMI link.
5. This bit has no impact on messages forwarded to/through the
device (for example, messages forwarded through a PCI-to-PCI
bridge to PCI Express link)
5RWLB 0
Hide_Dev5
When set, hide Device 5
1. This bit has no impact on any configuration transactions that
target the secondary side of a device that is a PCI-to-PCI bridge.
2. This bit has no effect on JTAG initiated accesses to corresponding
device’s configuration space.
3. This bit has no impact on memory transactions targeting the
device or memory transactions forwarded through the device.
4. This bit has no impact on IO transactions forwarded through the
device to the PCI Express/DMI link.
5. This bit has no impact on messages forwarded to/through the
device (for example, messages forwarded through a PCI-to-PCI
bridge to PCI Express link)
4RWL 0
Hide_Dev4
When set, hide Device 4
1. This bit has no impact on any configuration transactions that
target the secondary side of the PCI-to-PCI bridge.
2. This bit has no effect on JTAG initiated accesses to corresponding
device’s configuration space.
3. This bit has no impact on memory transactions forwarded
through the device (for example, memory transactions forwarded
through the Device#0 p2p bridge, to the PCI Express link)
4. This bit has no impact on IO transactions forwarded through the
device to the PCI Express/DMI link.
5. This bit has no impact on messages forwarded to/through the
device (for example, messages forwarded through a PCI-to-PCI
bridge to PCI Express link)
(Sheet 2 of 3)
Register: DEVHIDE1
Device: 8
Function: 0
Offset: F0h
Bit Attr Default Description