Datasheet
Processor Integrated I/O (IIO) Configuration Registers
114 Datasheet, Volume 2
3.4.4.7 NCMEM.LIMIT—NCMEM Limit
Limit address of Intel QuickPath Interconnect non-coherent memory.
3.4.4.8 DEVHIDE1—Device Hide 1 Register
This register provides a method to hide the PCI configuration space of devices inside
the Integrated I/O, from the host initiated configuration accesses. This register does
not impact JTAG initiated accesses to the corresponding device’s configuration space.
When set (for each device), all PCI configuration accesses from Intel
QuickPath
Interconnect targeting the corresponding device’s configuration space inside the
Integrated I/O (IIO) are master aborted. When clear, configuration accesses targeting
the device’s configuration space are allowed.
Register: NCMEM.LIMIT
Device: 8
Function: 0
Offset: E4h
Bit Attr Default Description
63:26 RW 0
Non-Coherent Memory Limit Address
Describes the limit address of a 64-MB aligned DRAM memory region on
Intel
QuickPath Interconnect that is non-coherent. Address bits [63:26] of
an inbound address if it satisfies ‘NcMem.Base[63:26] <= A[63:26] <=
NcMem.Limit[63:26]’ is considered to be towards the non-coherent Intel
QuickPath Interconnect memory region. It is expected that the range
indicated by the non-coherent memory base and limit registers is a subset
of either the low DRAM or high DRAM memory regions as described using
the corresponding base and limit registers.
This register is programmed once at boot time and does not change after
that.
25:0 RV 0 Reserved
(Sheet 1 of 3)
Register: DEVHIDE1
Device: 8
Function: 0
Offset: F0h
Bit Attr Default Description
31:28 RV 0 Reserved
27 RWL 0
Hide_Dev16_Fun1
When set, hide Device #16/Function #1
When set, all PCI configuration accesses from Intel QuickPath
Interconnect targeting the corresponding device’s configuration space
inside IIO are master aborted. When clear, configuration accesses
targeting the device’s configuration space are allowed.
This bit has no effect on smbus and jtag initiated accesses to
corresponding device’s configuration space.
The lock bit is lock1 (“TXTLOCK: TXT Lock Register”)