Datasheet

Processor Integrated I/O (IIO) Configuration Registers
112 Datasheet, Volume 2
3.4.4.2 IIOMISCSS—Integrated I/O MISC Status
This register can be used to read the status of Integrated I/O strapping pins.
3.4.4.3 TSEGCTRL—TSEG Control Register
The location of the TSEG region, size, and enable/disable control.
Register: IIOMISCSS
Device: 8
Function: 0
Offset: 9Ch
Bit Attr Default Description
31:5 RO 0 Reserved
4RO 1bReserved
3RO 1bReserved
2:0 RO Strap
CFG[2:0] Strap (Port Bifurcation)
111 = x16 (default)
110 = x8x8
101 = Reserved
Others = Reserved
Register: TSEGCTRL
Device: 8
Function: 0
Offset: A8h
Bit Attr Default Description
31:20 RWO FE0h
TBA: TSEG Base Address
Indicates the base address which is aligned to a 1-MB boundary. Bits
[31:20] corresponds to A[31:20] address bits.
19:4 RV 0 Reserved
3:1 RWO 100
TSEG_SIZE: Size of TSEG
000 = 512 KB
001 = 1 MB
010 = 2 MB
011 = 4 MB
100 = 8 MB
Others = Reserved
0RWO 1
TSEG_EN: TSEG Enabling Control
0 = Disabling the TSEG in IIO.
1 = Enabling the TSEG in IIO for IB access check.