Datasheet
Datasheet, Volume 2 11
MC_RIR_WAY_CH1_26; MC_RIR_WAY_CH1_27
MC_RIR_WAY_CH1_28; MC_RIR_WAY_CH1_29
MC_RIR_WAY_CH1_30; MC_RIR_WAY_CH1_31........................................ 267
4.13 Memory Thermal Control.................................................................................. 268
4.13.1 MC_THERMAL_CONTROL0
MC_THERMAL_CONTROL1 ..................................................................... 268
4.13.2 MC_THERMAL_STATUS0
MC_THERMAL_STATUS1........................................................................ 268
4.13.3 MC_THERMAL_DEFEATURE0
MC_THERMAL_DEFEATURE1 .................................................................. 269
4.13.4 MC_THERMAL_PARAMS_A0
MC_THERMAL_PARAMS_A1.................................................................... 269
4.13.5 MC_THERMAL_PARAMS_B0
MC_THERMAL_PARAMS_B1.................................................................... 270
4.13.6 MC_COOLING_COEF0
MC_COOLING_COEF1 ........................................................................... 270
4.13.7 MC_CLOSED_LOOP0
MC_CLOSED_LOOP1............................................................................. 271
4.13.8 MC_THROTTLE_OFFSET0
MC_THROTTLE_OFFSET1....................................................................... 271
4.13.9 MC_RANK_VIRTUAL_TEMP0
MC_RANK_VIRTUAL_TEMP1................................................................... 272
4.13.10MC_DDR_THERM_COMMAND0
MC_DDR_THERM_COMMAND1 ............................................................... 272
4.13.11MC_DDR_THERM_STATUS0
MC_DDR_THERM_STATUS1 ................................................................... 273
5 System Address Map ............................................................................................. 275
5.1 Introduction ................................................................................................... 275
5.2 Memory Address Space.................................................................................... 276
5.2.1 System Address Map ............................................................................ 277
5.2.2 System DRAM Memory Regions.............................................................. 278
5.2.3 VGA/SMM and Legacy C/D/E/F Regions ................................................... 279
5.2.3.1 VGA/SMM Memory Space......................................................... 279
5.2.3.2 C/D/E/F Segments.................................................................. 280
5.2.4 Address Region between 1 MB and TOLM................................................. 280
5.2.4.1 Relocatable TSEG.................................................................... 281
5.2.5 Address Region from TOLM to 4 GB ........................................................ 281
5.2.5.1 PCI Express
®
Memory Mapped Configuration Space..................... 281
5.2.5.2 MMIOL .................................................................................. 282
5.2.5.3 Miscellaneous......................................................................... 282
5.2.5.4 Processor Local CSR, On-die ROM, and Processor PSeg ................ 282
5.2.5.5 Legacy/HPET/TXT/TPM/Others.................................................. 282
5.2.5.6 Local XAPIC ........................................................................... 283
5.2.5.7 High BIOS Area ...................................................................... 283
5.2.5.8 INTA/Rsvd ............................................................................. 283
5.2.5.9 Firmware............................................................................... 283
5.2.6 Address Regions above 4 GB.................................................................. 284
5.2.6.1 High System Memory .............................................................. 284
5.2.6.2 Memory Mapped IO High.......................................................... 284
5.2.6.3 BIOS Notes on Address Allocation above 4 GB ............................ 285
5.2.7 Protected System DRAM Regions............................................................ 285
5.3 IO Address Space............................................................................................ 285
5.3.1 VGA I/O Addresses............................................................................... 285
5.3.2 ISA Addresses ..................................................................................... 286
5.3.3 CFC/CF8 Addresses .............................................................................. 286
5.3.4 PCIe Device I/O Addresses .................................................................... 286
5.4 Configuration/CSR Space.................................................................................. 286
5.4.1 PCIe Configuration Space ...................................................................... 286