Datasheet

Datasheet, Volume 2 107
Processor Integrated I/O (IIO) Configuration Registers
3.4.3.4 DEVCAP—PCI Express
®
Device Capabilities Register
The PCI Express Device Capabilities register identifies device specific information for
the device.
Device: 8
Function: 0, 1, 2
Offset: 44h
Bit Attr Default Description
31:28 RO 0h Reserved
27:26 RO 0h
Captured Slot Power Limit Scale
Does not apply to root ports or integrated devices.
25:18 RO 00h
Captured Slot Power Limit Value
Does not apply to root ports or integrated devices.
17:16 RO 0h Reserved
15 RO 1
Role Based Error Reporting
Integrated I/O is 1.1 compliant and so supports this feature.
14 RO 0
Power Indicator Present on Device
Does not apply to root ports or integrated devices.
13 RO 0
Attention Indicator Present
Does not apply to root ports or integrated devices.
12 RO 0
Attention Button Present
Does not apply to root ports or integrated devices.
11:9 RO 000
Endpoint L1 Acceptable Latency
Does not apply to Integrated I/O.
8:6 RO 000
Endpoint L0s Acceptable Latency
Does not apply to Integrated I/O.
5RO 0
Extended Tag Field Supported
Integrated I/O devices support only 5-bit tag field.
4:3 RO 0h
Phantom Functions Supported
Integrated I/O does not support phantom functions.
2:0 RO 000
Max Payload Size Supported
Integrated I/O supports 256B payloads on Express port and 128B on the
reminder of the devices.