Datasheet

Datasheet, Volume 2 103
Processor Integrated I/O (IIO) Configuration Registers
3.4.2.5 RID—Revision Identification Register
This register contains the revision number of the Integrated I/O.
3.4.2.6 CCR—Class Code Register
This register contains the Class Code for the device.
3.4.2.7 CLSR—Cacheline Size Register
Register: RID
Device: 8
Function: 0-3
Offset: 08h
Bit Attr Default Description
7:4 RO
See
description
Minor Revision
Steppings which required all masks be regenerated. Refer to the Intel
®
Core™ i7-800 and i5-700 Desktop Processor Series Speci
fication Update
for the value of the Revision ID Register.
3:0 RO
See
description
Minor Revision Identification Number (RID)
Increment for each steppings which do not require masks to be regenerated.
Refer to the Intel
®
Core™ i7-800 and i5-700 Desktop Processor Series
Speci
fication Update for the value of the Revision ID Register.
Register: CCR
Device: 8
Function: 0-3
Offset: 09h
Bit Attr Default Description
23:16 RO 08h
BaseClass
Provides the PCI Express base class type. Most common registers will default
to 08h. (Base system peripherals.)
15:8 RO 80h
SubClass
This field defaults to 80h indicating other system peripherals in PCI v3.0 class
code mnemonic).
7:0 RO 00h
Register-Level Programming Interface
This field is hardwired to 00h.
Register: CLSR
Device: 8
Function: 0-2
Offset: 0Ch
Bit Attr Default Description
7:0 RW 0
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for
Integrated I/O is always 64B. IIO hardware ignore this setting.