Datasheet

10 Datasheet, Volume 2
4.10.28MC_CHANNEL_0_EW_BGF_SETTINGS
MC_CHANNEL_1_EW_BGF_SETTINGS......................................................257
4.10.29MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS
MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS .........................................258
4.10.30MC_CHANNEL_0_ROUND_TRIP_LATENCY
MC_CHANNEL_1_ROUND_TRIP_LATENCY.................................................258
4.10.31MC_CHANNEL_0_PAGETABLE_PARAMS1
MC_CHANNEL_1_PAGETABLE_PARAMS1 ..................................................259
4.10.32MC_CHANNEL_0_PAGETABLE_PARAMS2
MC_CHANNEL_1_PAGETABLE_PARAMS2 ..................................................259
4.10.33MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0
MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1.......................................260
4.10.34MC_TX_BG_CMD_OFFSET_SETTINGS_CH0
MC_TX_BG_CMD_OFFSET_SETTINGS_CH1...............................................260
4.10.35MC_TX_BG_DATA_OFFSET_SETTINGS_CH0
MC_TX_BG_DATA_OFFSET_SETTINGS_CH1 .............................................260
4.11 Integrated Memory Controller Channel Address Registers......................................261
4.11.1 MC_DOD_CH0_0
MC_DOD_CH0_1 ..................................................................................261
4.11.2 MC_DOD_CH1_0
MC_DOD_CH1_1 ..................................................................................262
4.11.3 MC_SAG_CH0_0; MC_SAG_CH0_1; MC_SAG_CH0_2; MC_SAG_CH0_3;
MC_SAG_CH0_4; MC_SAG_CH0_5; MC_SAG_CH0_6; MC_SAG_CH0_7........263
4.11.4 MC_SAG_CH1_0; MC_SAG_CH1_1; MC_SAG_CH1_2; MC_SAG_CH1_3;
MC_SAG_CH1_4; MC_SAG_CH1_5; MC_SAG_CH1_6; MC_SAG_CH1_7........264
4.12 Integrated Memory Controller Channel Rank Registers..........................................265
4.12.1 MC_RIR_LIMIT_CH0_0; MC_RIR_LIMIT_CH0_1; MC_RIR_LIMIT_CH0_2;
MC_RIR_LIMIT_CH0_3; MC_RIR_LIMIT_CH0_4; MC_RIR_LIMIT_CH0_5;
MC_RIR_LIMIT_CH0_6; MC_RIR_LIMIT_CH0_7 ........................................265
4.12.2 MC_RIR_LIMIT_CH1_0; MC_RIR_LIMIT_CH1_1; MC_RIR_LIMIT_CH1_2;
MC_RIR_LIMIT_CH1_3; MC_RIR_LIMIT_CH1_4; MC_RIR_LIMIT_CH1_5;
MC_RIR_LIMIT_CH1_6; MC_RIR_LIMIT_CH1_7 ........................................265
4.12.3 MC_RIR_WAY_CH0_0; MC_RIR_WAY_CH0_1; MC_RIR_WAY_CH0_2;
MC_RIR_WAY_CH0_3; MC_RIR_WAY_CH0_4; MC_RIR_WAY_CH0_5
MC_RIR_WAY_CH0_6; MC_RIR_WAY_CH0_7
MC_RIR_WAY_CH0_8; MC_RIR_WAY_CH0_9
MC_RIR_WAY_CH0_10; MC_RIR_WAY_CH0_11
MC_RIR_WAY_CH0_12; MC_RIR_WAY_CH0_13
MC_RIR_WAY_CH0_14; MC_RIR_WAY_CH0_15
MC_RIR_WAY_CH0_16; MC_RIR_WAY_CH0_17
MC_RIR_WAY_CH0_18; MC_RIR_WAY_CH0_19
MC_RIR_WAY_CH0_20; MC_RIR_WAY_CH0_21
MC_RIR_WAY_CH0_22; MC_RIR_WAY_CH0_23
MC_RIR_WAY_CH0_24; MC_RIR_WAY_CH0_25
MC_RIR_WAY_CH0_26; MC_RIR_WAY_CH0_27
MC_RIR_WAY_CH0_28; MC_RIR_WAY_CH0_29
MC_RIR_WAY_CH0_30; MC_RIR_WAY_CH0_31 ........................................266
4.12.4 MC_RIR_WAY_CH1_0; MC_RIR_WAY_CH1_1
MC_RIR_WAY_CH1_2; MC_RIR_WAY_CH1_3
MC_RIR_WAY_CH1_4; MC_RIR_WAY_CH1_5
MC_RIR_WAY_CH1_6; MC_RIR_WAY_CH1_7
MC_RIR_WAY_CH1_8; MC_RIR_WAY_CH1_9
MC_RIR_WAY_CH1_10; MC_RIR_WAY_CH1_11
MC_RIR_WAY_CH1_12; MC_RIR_WAY_CH1_13
MC_RIR_WAY_CH1_14; MC_RIR_WAY_CH1_15
MC_RIR_WAY_CH1_16; MC_RIR_WAY_CH1_17
MC_RIR_WAY_CH1_18; MC_RIR_WAY_CH1_19
MC_RIR_WAY_CH1_20; MC_RIR_WAY_CH1_21
MC_RIR_WAY_CH1_22; MC_RIR_WAY_CH1_23
MC_RIR_WAY_CH1_24; MC_RIR_WAY_CH1_25