Intel® Core™ i7-800 and i5-700 Desktop Processor Series Datasheet – Volume 2 September 2009 Document Number: 322165-001
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Contents 1 Introduction ............................................................................................................ 17 1.1 Register Terminology ......................................................................................... 17 2 Configuration Process and Registers ....................................................................... 19 2.1 Platform Configuration Structure ......................................................................... 19 2.1.
3.3.4.2 3.3.4.3 3.3.4.4 3.3.4.5 3.4 4 SNXTPTR—Subsystem ID Next Pointer .........................................51 SVID—Subsystem Vendor ID ......................................................52 SID—Subsystem Identity ...........................................................52 DMIRCBAR—DMI Root Complex Register Block Base Address Register ...................................................................................52 3.3.4.6 MSICAPID—MSI Capability ID ..........................................
3.4.3 3.4.4 3.4.5 Datasheet, Volume 2 3.4.2.4 PCISTS—PCI Status Register .................................................... 101 3.4.2.5 RID—Revision Identification Register ......................................... 103 3.4.2.6 CCR—Class Code Register ........................................................ 103 3.4.2.7 CLSR—Cacheline Size Register.................................................. 103 3.4.2.8 HDR—Header Type Register ..................................................... 104 3.4.2.
3.4.6 3.4.7 3.5 6 Intel® 3.5.1 3.5.2 3.4.5.8 CWR[4:7]—Conditional Write Registers 4-7................................. 130 3.4.5.9 CWR[8:11]—Conditional Write Registers 8-11 ............................. 130 3.4.5.10 CWR[12:15]—Conditional Write Registers 12-15.......................... 130 3.4.5.11 CWR[16:17]—Conditional Write Registers 16-17.......................... 131 3.4.5.12 CWR[18:23]—Conditional Write Registers 18-23.......................... 131 3.4.5.13 IR[0:3]—Increment Registers 0-3.......
3.6 Intel® 3.6.1 3.7 Intel® 3.7.1 3.7.2 4 3.5.2.26 INTR_REMAP_TABLE_BASE[0:1]—Interrupt Remapping Table Base Address Register..................................................... 154 3.5.2.27 FLTREC[10,7:0]—Fault Record Register ..................................... 155 3.5.2.28 INVADDRREG[0:1]—Invalidate Address Register ......................... 155 3.5.2.29 IOTLBINV[0:1]—IOTLB Invalidate Register ................................. 156 Trusted Execution Technology (Intel® TXT) Register Map ..........
4.5 4.6 4.7 4.8 4.9 8 4.4.3.2 Compatible Revision ID (CRID) ................................................. 203 4.4.4 CCR—Class Code Register ...................................................................... 204 4.4.5 HDR—Header Type Register ................................................................... 205 4.4.6 SVID—Subsystem Vendor Identification Register....................................... 205 4.4.7 SID—Subsystem Identity .............................................................
4.10 4.9.9 MC_TEST_PAT_IS................................................................................. 235 4.9.10 MC_TEST_PAT_DCD ............................................................................. 235 4.9.11 MC_TEST_EP_SCCTL............................................................................. 236 4.9.12 MC_TEST_EP_SCD................................................................................ 236 Integrated Memory Controller Channel Control Registers .............................
4.11 4.12 10 4.10.28MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS...................................................... 257 4.10.29MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS ......................................... 258 4.10.30MC_CHANNEL_0_ROUND_TRIP_LATENCY MC_CHANNEL_1_ROUND_TRIP_LATENCY................................................. 258 4.10.31MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1 ..................................................
4.13 5 MC_RIR_WAY_CH1_26; MC_RIR_WAY_CH1_27 MC_RIR_WAY_CH1_28; MC_RIR_WAY_CH1_29 MC_RIR_WAY_CH1_30; MC_RIR_WAY_CH1_31........................................ 267 Memory Thermal Control .................................................................................. 268 4.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 ..................................................................... 268 4.13.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1........................................................................
5.5 5.6 5.7 5.8 12 System Management Mode (SMM) ..................................................................... 287 5.5.1 SMM Space Definition ............................................................................ 287 5.5.2 SMM Space Restrictions ......................................................................... 288 5.5.3 SMM Space Combinations ...................................................................... 288 5.5.4 SMM Control Combinations......................................
Figures 2-1 2-2 3-1 3-2 4-1 5-1 5-2 5-3 Memory Map to PCI Express* Device Configuration Space....................................... 22 Processor Configuration Cycle Flowchart ............................................................... 23 DMI Port (Device 0) and PCI Express* Root Ports Type 1 Configuration Space ........... 29 Base Address of Intel® VT-d Remap Engines ....................................................... 137 Padscan Accessibility Mechanism ............................................
4-13 Device 4, Function 3 — Integrated Memory Controller Channel 0 Thermal Control Registers................................................................................. 196 4-14 Device 5, Function 0 — Integrated Memory Controller Channel 1 Control Registers ............................................................................................. 197 4-15 Device 5, Function 1 — Integrated Memory Controller Channel 1 Address Registers ..................................................................
Revision History Revision Number -001 Description Revision Date September 2009 Initial release § Datasheet, Volume 2 15
Datasheet, Volume 2
Introduction 1 Introduction This is Volume 2 of the Datasheet for the Intel® Core™ i7-800 and i5-700 desktop processor series. The processor contains one or more PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket. This document describes these configuration space registers or device-specific control and status registers (CSRs) only.
Introduction Term Description RWO Read/Write Once. A register bit with this attribute can be written to only once after power up. After the first write, the bit becomes read only. This attribute is applied on a bit by bit basis. For example, if the RWO attribute is applied to a 2-bit field, and only one bit is written, then the written bit cannot be rewritten (unless reset). The unwritten bit, of the field, may still be written once. This is special case of RWL. RWDS RRW L RSVD/RV RW and Sticky.
Configuration Process and Registers 2 Configuration Process and Registers 2.1 Platform Configuration Structure The DMI physically connects the processor and the Intel Platform Controller Hub (PCH). From a configuration standpoint, the DMI is logically PCI Bus 0. A physical PCI Bus 0 does not exist. DMI and the internal devices in the processor Integrated I/O (IIO) and Intel PCH logically constitute PCI Bus 0 to configuration software.
Configuration Process and Registers Control/Status registers and Function 4 contains miscellaneous control/status registers on power management and throttling. • Device 16 — Intel® QuickPath Interconnect. Device 16, Function 0 contains the Intel® QuickPath Interconnect configuration registers for Intel QuickPath Interconnect Link. Device 16, Function 1 contains the routing and protocol. 2.1.
Configuration Process and Registers 2.2 Configuration Mechanisms The processor is the originator of configuration cycles. Internal to the processor transactions received through both of the below configuration mechanisms are translated to the same format. 2.2.1 Standard PCI Express* Configuration Mechanism The following is the mechanism for translating processor I/O bus cycles to configuration cycles.
Configuration Process and Registers the base address for the block of addresses below 4 GB for the configuration space associated with busses, devices and functions that are potentially a part of the PCI Express root complex hierarchy. In the SAD_PCIEXBAR register there exists controls to limit the size of this reserved memory mapped space. 256 MB is the amount of address space required to reserve space for every bus, device, and function that could possibly exist.
Configuration Process and Registers 2.3 Routing Configuration Accesses The processor supports two PCI related interfaces: DMI and PCI Express. The processor is responsible for routing PCI and PCI Express configuration cycles to the appropriate device that is an integrated part of the processor or to one of these two interfaces. Configuration cycles to the PCH internal devices and Primary PCI (including downstream devices) are routed to the PCH using DMI.
Configuration Process and Registers 2.3.1 Internal Device Configuration Accesses The processor decodes the Bus Number (Bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the configuration cycle is targeting a PCI Bus 0 device. If the targeted PCI Bus 0 device exists in the processor and is not disabled, the configuration cycle is claimed by the appropriate device. 2.3.
Configuration Process and Registers 2.3.2.2 DMI Configuration Accesses Accesses to disabled processor internal devices, bus numbers not claimed by the HostPCI Express bridge, or PCI Bus 0 devices not part of the processor will subtractively decode to the PCH and consequently be forwarded over the DMI using a PCI Express configuration TLP.
Configuration Process and Registers In addition to reserved bits within a register, the processor contains address locations in the configuration space of the Host Bridge entity that are marked either "Reserved" or “Intel Reserved”. The processor responds to accesses to “Reserved” address locations by completing the host cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved” registers can be 8, 16, or 32 bits in size).
Processor Integrated I/O (IIO) Configuration Registers 3 Processor Integrated I/O (IIO) Configuration Registers 3.1 Processor IIO Devices (PCI Bus 0) The processor Integrated I/O (IIO) contains the following PCI devices within a single, physical component. The configuration registers for the devices are mapped as devices residing on PCI Bus 0. • Device 0 — DMI Root Port. Logically this appears as a PCI device residing on PCI Bus 0.
Processor Integrated I/O (IIO) Configuration Registers 3.2 Device Mapping All devices on the Integrated I/O Module reside on PCI Bus 0. Table 3-1 describes the devices and functions that the integrated I/O (IIO) module implements or routes specifically. Table 3-1. Functions Handled by the Processor Integrated I/O (IIO) Register Group DMI 3.2.
Processor Integrated I/O (IIO) Configuration Registers treated as static in the sense that they will not be changed without the decode control bits being clear. Registers outside of this standard space will be noted as dynamic when appropriate. 3.3.2 Configuration Register Map Figure 3-1.
Processor Integrated I/O (IIO) Configuration Registers Figure 3-1 illustrates how each PCI Express port’s configuration space appears to software. Each PCI Express configuration space has three regions: • Standard PCI Header — This region is the standard PCI-to-PCI bridge header providing legacy OS compatibility and resource management. • PCI Device Dependent Region — This region is also part of standard PCI configuration space and contains the PCI capability structures and other port specific registers.
Processor Integrated I/O (IIO) Configuration Registers Table 3-2.
Processor Integrated I/O (IIO) Configuration Registers Table 3-3.
Processor Integrated I/O (IIO) Configuration Registers Table 3-4.
Processor Integrated I/O (IIO) Configuration Registers Table 3-5.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3 Standard PCI Configuration Space (0h to 3Fh) — Type 0/1 Common Configuration Space This section covers registers in the 0h to 3Fh region that are common to devices 0, 3,5. Comments at the top of the table indicate what devices/functions the description applies to. Exceptions that apply to specific functions are noted in the individual bit descriptions. 3.3.3.1 VID—Vendor Identification Register Register: Device: Function: Offset: 3.3.3.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.3 PCICMD—PCI Command Register This register defines the PCI 3.0 compatible command register values applicable to PCI Express space. Register: Device: Function: Offset: 36 PCICMD 0 (DMI) 0 04h Bit Attr Default Description 15:11 RV 00h 10 RW 0 Legacy Interrupt Mode Enable/Disable 9 RO 0 Fast Back-to-Back Enable Not applicable. Hardwired to 0.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 1 of 2) Register: Device: Function: Offset: Bit Attr Default 15:11 RV 00h 10 RW 0 Legacy Interrupt Mode Enable/Disable 9 RO 0 Fast Back-to-Back Enable Not applicable to PCI Express and is hardwired to 0. Description Reserved (by PCI SIG) 8 RW 0 SERR Enable For PCI Express/DMI ports, this field enables notifying the internal core error logic of occurrence of an uncorrectable error (fatal or non-fatal) at the port.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Register: Device: Function: Offset: Bit 1 0 3.3.3.4 PCICMD 3,5 (PCIe*) 0 04h Attr RW RW Default Description 0 Memory Space Enable (MSE) 0 = Disables a PCI Express port’s memory range registers (including the CSR range registers) to be decoded as valid target addresses for transactions from primary side.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Register: Device: Function: Offset: Bit 13 12 Datasheet, Volume 2 PCISTS 0 (DMI), 3,5 (PCIe) 0 06h Attr RW1C RW1C Default Description 0 Received Master Abort Status This bit is set when a device experiences a master abort condition on a transaction it mastered on the primary interface (Integrated I/O internal bus).
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.5 RID—Revision Identification Register This register contains the revision number of the Integrated I/O. Register: Device: Function: Offset: RID 0 (DMI), 3,5 (PCIe) 0 08h Bit Attr 7:4 RWO Default Description Minor Revision See Steppings that required all masks be regenerated. Refer to the Intel® Description Core™ i7-800 and i5-700 Desktop Processor Series Specification Update for the value of the Revision ID Register.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.7 CLSR—Cacheline Size Register Register: Device: Function: Offset: 3.3.3.8 CLSR 0 (DMI), 3,5 (PCIe) 0 0Ch Bit Attr Default 7:0 RW 0h Description Cacheline Size This register is set as RW for compatibility reasons only. Cacheline size for Integrated I/O is always 64B. Hardware ignores this setting.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.10 SVID—Subsystem Vendor ID This register identifies the vendor of the subsystem. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Register: Device: Function: Offset: 3.3.3.11 SVID 0 (DMI) 0 2Ch Bit Attr Default 15:0 RWO 8086h Description Subsystem Vendor Identification This field is programmed during boot-up to indicate the vendor of the system board.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.14 INTPIN—Interrupt Pin Register The INTP register identifies legacy interrupts for INTA, INTB, INTC, and INTD as determined by BIOS/firmware. Register: Device: Function: Offset: Bit 7:0 3.3.3.15 INTPIN 0 (DMI), 3,5 (PCIe) 0 3Dh Attr RWO Default Description 01h INTP: Interrupt Pin This field defines the type of interrupt to generate for the PCI Express port.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.17 SUBBUS—Subordinate Bus Number Register This register identifies the subordinate bus (if any) that resides at the level below the secondary bus of the PCI Express interface. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to devices subordinate to the secondary PCI Express port. Register: SUBBUS Device: 3,5 (PCIe) Function: 0 Offset: 1Ah Bit 7:0 3.3.3.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.19 IOLIM—I/O Limit Register The I/O Base register defines an address range that is used by the PCI Express port to determine when to forward I/O transactions from one interface to the other using the following formula: IO_BASE ≤ A[15:12] ≤ IO_LIMIT The bottom of the defined I/O address range will be aligned to a 4-KB (1-KB if EN1K bit is set.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.20 SECSTS—Secondary Status Register Secondary Status register is a 16-bit status register that reports the occurrence of various events associated with secondary side (that is, PCI Express/DMI side) of the “virtual” PCI-to-PCI bridge.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.21 MBAS—Memory Base The Memory Base and Memory Limit registers define a memory-mapped I/O nonprefetchable address range (32-bit addresses) and the Integrated I/O directs accesses in this range to the PCI Express port based on the following formula: MEMORY_BASE ≤ A[31:20] ≤ MEMORY_LIMIT The upper 12 bits of both the Memory Base and Memory Limit registers are read/write and corresponds to the upper 12 address bits, A[31:20] of 32-bit addresses.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.25 PMBASEU—Prefetchable Memory Base (Upper 32 bits) The Prefetchable Base Upper 32-bits and Prefetchable Limit Upper 32-bits registers are extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers to support a 64-bit prefetchable memory address range. Register: Device: Function: Offset: Bit 31:0 3.3.3.
Processor Integrated I/O (IIO) Configuration Registers 3.3.3.27 BCTRL—Bridge Control Register The Bridge Control register provides additional control for the secondary interface (that is, PCI Express) as well as some bits that affect the overall behavior of the “virtual” PCI-to-PCI bridge embedded within the Integrated I/O, for example, VGA-compatible address range mapping.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Register: Device: Function: Offset: Bit 2 BCTRL 3,5 (PCIe) 0 3Eh Attr RW Default Description 0 ISA Enable This bit modifies the response by the Integrated I/O to an I/O access issued by the processor that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIM registers. 0 = All addresses defined by the IOBASE and IOLIM for processor I/O transactions will be mapped to PCI Express.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.3 SVID—Subsystem Vendor ID Register: Device: Function: Offset: 3.3.4.4 Bit Attr Default Description 15:0 RWO 8086h Subsystem Vendor Identification This field is programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes read only. SID—Subsystem Identity Register: Device: Function: Offset: 3.3.4.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.6 MSICAPID—MSI Capability ID Register: Device: Function: Offset: 3.3.4.7 Bit Attr Default 7:0 RO 05h Description Capability Identifier Assigned by PCI-SIG for MSI (root ports). MSINXTPTR—MSI Next Pointer Register: Device: Function: Offset: 3.3.4.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.9 MSIAR—MSI Address Register The MSI Address Register (MSIAR) contains the system specific address information to route MSI interrupts from the root ports and is broken into its constituent fields. Register: Device: Function: Offset: 54 MSIAR 0 (DMI), 3,5 (PCIe) 0 64h Bit Attr Default Description 31:20 RW 0h Address MSB This field specifies the 12 most significant bits of the 32-bit MSI address.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.10 MSIDR—MSI Data Register The MSI Data Register contains all the data (interrupt vector) related to MSI interrupts from the root ports. Register: Device: Function: Offset: Bit Attr Default 31:16 RO 0000h Reserved 15:14 RW 0h Reserved 13:12 RW 0h Reserved 0h Delivery Mode 0000 = Fixed: Trigger Mode can be edge or level. 0001 = Lowest Priority: Trigger Mode can be edge or level.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.12 MSIPENDING—MSI Pending Bit Register The Mask Pending register enables software to defer message sending on a per-vector basis. Register: Device: Function: Offset: 3.3.4.13 MSIPENDING 0 (DMI), 3,5 (PCIe) 0 70h Bit Attr Default Description 31:2 RV 0h Reserved 1:0 RO 0h Pending Bit For each Pending bit that is set, the PCI Express port has a pending associated message.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.15 PEGCAP—PCI Express* Capabilities Register The PCI Express Capabilities register identifies the PCI Express device type and associated capabilities. Register: Device: Function: Offset: PEGCAP 0 (DMI), 3,5 (PCIe) 0 92h Bit Attr Default 15:14 RV 0h 13:9 Datasheet, Volume 2 RO Description Reserved 00h Interrupt Message Number Applies only to the root ports.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.16 DEVCAP—PCI Express* Device Capabilities Register The PCI Express Device Capabilities register identifies device specific information for the device. Register: Device: Function: Offset: Bit Attr Default 31:28 RV 0h Reserved 27:26 RO 0h Captured Slot Power Limit Scale Does not apply to root ports or integrated devices. 25:18 RO 00h Captured Slot Power Limit Value Does not apply to root ports or integrated devices.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.17 DEVCTRL—PCI Express* Device Control Register The PCI Express Device Control register controls PCI Express specific capabilities parameters associated with the device.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Register: Device: Function: Offset: Bit 1 0 60 DEVCTRL 0 (DMI), 3,5 (PCIe) 0 98h Attr RW RW Default Description 0 Non Fatal Error Reporting Enable Applies only to the PCI Express/DMI ports. Controls the reporting of non-fatal errors that Integrated I/O detects on the PCI Express/DMI interface. 0 = Reporting of Non Fatal error detected by device is disabled. 1 = Reporting of Non Fatal error detected by device is enabled.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.18 DEVSTS—PCI Express* Device Status Register The PCI Express Device Status register provides information about PCI Express device specific parameters associated with the device. Register: Device: Function: Offset: Bit Attr Default 15:6 RV 000h 5 RO 0h 4 RO 0 Reserved 0 Unsupported Request Detected This bit applies only to the root/DMI ports.This bit indicates that the root port detected an Unsupported Request.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.19 LNKCAP—PCI Express* Link Capabilities Register The Link Capabilities register identifies the PCI Express specific link capabilities. (Sheet 1 of 2) Register: Device: Function: Offset: Bit Attr Default 31:24 RWO 0 23:22 RV 0h 21 RO 1 Link Bandwidth Notification Capability A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Register: Device: Function: Offset: Bit 9:4 3:0 Datasheet, Volume 2 LNKCAP 0 (DMI), 3,5 (PCIe) 0 9Ch Attr Default RWO 010000b RWO Dev 3,5: See description Dev 3,5: See description Dev 0: 0001b Description Maximum Link Width This field indicates the maximum width of the given PCI Express Link attached to the port.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.20 LNKCON—PCI Express* Link Control Register (Device 0) The PCI Express Link Control register controls the PCI Express Link specific parameters. Register: Device: Function: Offset: Bit Attr Default 15:12 RV 0 Reserved 11 RO 0 Link Autonomous Bandwidth Interrupt Enable When set to 1, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.21 LNKCON—PCI Express* Link Control Register The PCI Express Link Control register controls the PCI Express Link specific parameters. Register: Device: Function: Offset: LNKCON 3, 5 (PCIe) 0 A0h Bit Attr Default 15:12 RV 0 Reserved 11 RW 0 Link Autonomous Bandwidth Interrupt Enable When set to 1, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.22 LNKSTS—PCI Express* Link Status Register The PCI Express Link Status register provides information on the status of the PCI Express Link such as negotiated width, training, and so forth.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Register: Device: Function: Offset: Bit 9:4 3:0 Datasheet, Volume 2 LNKSTS 0 (DMI), 3, 5 (PCIe) 0 A2h Attr RO RO Default Description 0h Negotiated Link Width This field indicates the negotiated width of the given PCI Express link after training is completed. Only x8 and x16 link width negotiations are supported in Integrated I/O.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.23 SLTCAP—PCI Express* Slot Capabilities Register The Slot Capabilities register identifies the PCI Express specific slot capabilities. These registers must be ignored by software on the DMI links. Note: Hot-plug for PCIe is not supported on Desktop, Platforms.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.24 SLTCON—PCI Express* Slot Control Register The Slot Control register identifies the PCI Express specific slot control parameters for operations such as Power Management.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.25 ROOTCON—PCI Express* Root Control Register The PCI Express Root Control register specifies parameters specific to the root complex port. (Sheet 1 of 2) Register: Device: Function: Offset: Bit Attr Default 15:5 RV 0h Reserved 0h CRS Software Visibility Enable When set to 1, this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software. If 0, retry status cannot be returned to software.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Register: Device: Function: Offset: Bit 0 3.3.4.26 ROOTCON 0 (DMI), 3, 5 (PCIe) 0 ACh Attr RW Default Description 0h System Error on Correctable Error Enable This field controls notifying the internal core error logic of the occurrence of a correctable error in the device or below its hierarchy. The internal core error logic of Integrated I/O then decides if/how to escalate the error further (pins/message, and so forth).
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.27 ROOTSTS—PCI Express* Root Status Register The PCI Express Root Status register specifies parameters specific to the root complex port. Register: Device: Function: Offset: Bit Attr Default 31:18 RV 0h Reserved 0h PME Pending This field indicates that another PME is pending when the PME Status bit is set.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.28 DEVCAP2—PCI Express* Device Capabilities Register 2 Register: Device: Function: Offset: Bit Attr Default 31:6 RO 0h 5 RO 1 Alternative RID Interpretation (ARI) Capable This bit is set to 1b indicating Root Port supports this capability. 4 RO 1 Completion Time-out Disable Supported IIO supports disabling completion time-out.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.29 DEVCTRL2—PCI Express* Device Control Register 2 Register: Device: Function: Offset: Bit Attr Default 15:6 RO 0h 5 RW 0 Alternative RID Interpretation (ARI) Enable When set to 1b, ARI is enabled for the Root Port. 0 Completion Time-out Disable 1 = Disables the Completion Time-out mechanism for all NP tx that IIO issues on the PCI Express/DMI link. 0 = Completion time-out is enabled.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.30 LNKCON2—PCI Express* Link Control Register 2 Register: Device: Function: Offset: LNKCON2 0 (DMI), 3, 5 (PCIe) 0 C0h Bit Attr Default 15:13 RO 0 Reserved 12 RWS 0 Compliance De-Emphasis This bit sets the de-emphasis level in Polling Compliance state if the entry occurred due to the Enter Compliance bit being 1b. 1b = 3.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.31 LNKSTS2—PCI Express* Link Control Register 2 Register: Device: Function: Offset: Bit Attr Default 15:1 RO 0 Reserved 0 Compliance De-Emphasis Current de-emphasis level - when operating at Gen2 speed. This is unused in Gen1 speed. 1b = 3.5 dB 0b = 6 dB 0 3.3.4.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.33 PMCSR—Power Management Control and Status Register (Device 0 DMI) This register provides status and control information for PM events on the DMI port.. . Register: Device: Function: Offset: PMCSR 0 (DMI) 0 E4h Bit Attr Default Description 31:24 RO 00h 23 RO 0h Bus Power/Clock Control Enable This field is hardwired to 0h as it does not apply to PCI Express.
Processor Integrated I/O (IIO) Configuration Registers 3.3.4.34 PMCSR—Power Management Control and Status Register This register provides status and control information for PM events in the PCI Express ports of the Integrated I/O. Register: Device: Function: Offset: Bit Attr Default 31:24 RO 00h 23 RO 0h Bus Power/Clock Control Enable This field is hardwired to 0h as it does not apply to PCI Express.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5 PCIe/DMI Extended Configuration Space This section describes the extended configuration space (100h to 1FCh) for PCI Express and DMI ports. 3.3.5.1 APICBASE—APIC Base Register Register: Device: Function: Offset: 3.3.5.2 Bit Attr Default 15:12 RO 0h Reserved Description 11:1 RW 0h Bits 19:9 of the APIC Base Bits 31:20 are assumed to be FECh. Bits 8:0 are don’t care for address decode.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Register: Device: Function: Offset: Bit PERFCTRLSTS 0 (DMI), 3, 5 (PCIe) 0 180h Attr Default Description Number of Outstanding RFOs/Pre-Allocated Non-Posted Requests for PCI Express Gen1 This register controls the number of outstanding inbound non-posted requests - I/O, config, memory - that a Gen1 PCI Express downstream port can have, for all non-posted requests (peer-to-peer or to main-memory) it pre-allocates buffer space for.
Processor Integrated I/O (IIO) Configuration Registers 3.3.5.4 MISCCTRLSTS—Miscellaneous Control and Status Register (Sheet 1 of 3) Register: Device: Function: Offset: MISCCTRLSTS 0 (DMI), 3, 5 (PCIe) 0 188h Bit Attr Default Description 63:50 RO 0 49 RW1CS 0 Reserved Reserved 48 RW1C 0 Received PME_TO_ACK Indicates that Integrated I/O received a PME turn off ACK packet or it timed out waiting for the packet.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 3) Register: Device: Function: Offset: Bit Attr Default Description 27 RWS 0 System Interrupt Only on Link BW/Management Status This bit, when set, will disable generating MSI interrupt on link bandwidth (speed and/or width) and management changes, even if MSI is enabled that is, will disable generating MSI when LNKSTS Bits 15 and 14 are set.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 3 of 3) Register: Device: Function: Offset: 3.3.5.5 MISCCTRLSTS 0 (DMI), 3, 5 (PCIe) 0 188h Bit Attr Default Description 1 RWO 0h Inbound Configuration Enable When clear, all inbound configuration transactions are sent a UR response by the receiving PCI Express port. When set, inbound configs are allowed. Note: Enabling is only for debug purposes.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6 DMI Root Complex Register Block This block is mapped into memory space, using register DMIRCBAR [Dev0:F0, offset 50h]. Table 3-6.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.1 DMIVCH—DMI Virtual Channel Capability Header This register Indicates DMI Virtual Channel capabilities. BAR: Register: Offset: 3.3.6.2 DMIRCBAR DMIVCH 0000h Bit Attr Default Description 31:20 RO 040h Pointer to Next Capability (PNC) This field contains the offset to the next PCI Express capability structure in the linked list of capabilities (Link Declaration Capability).
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.3 DMIVCCAP2—DMI Port VC Capability Register 2 This register Describes the configuration of PCI Express Virtual Channels associated with this port. BAR: Register: Offset: Bit 3.3.6.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.5 DMIVC0RCAP—DMI VC0 Resource Capability BAR: Register: Offset: Bit 3.3.6.6 DMIRCBAR DMIVC0RCAP 0010h Attr Default Description 31:24 RO 0h 23 RO 0 22:16 RO 0h Reserved for Maximum Time Slots Reserved for Port Arbitration Table Offset Reserved 15 RO 0h Reject Snoop Transactions (REJSNPT) 0 = Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.7 DMIVC0RSTS—DMI VC0 Resource Status Reports the Virtual Channel specific status. BAR: Register: Offset: 3.3.6.8 Bit Attr Default 15:2 RO 0h Reserved. Reserved and Zero for future R/WC/S implementations. Software must use 0 for writes to these bits. Description 1 RO 1b Virtual Channel 0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.9 DMIVC1RCTL—DMI VC1 Resource Control Controls the resources associated with PCI Express Virtual Channel 1. BAR: Register: Offset: DMIRCBAR DMIVC1RCTL 0020h Bit Attr Default Description 31 RW 0 Virtual Channel 1 Enable (VC1E) 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled. See exceptions below. Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.10 DMIVC1RSTS—DMI VC1 Resource Status Reports the Virtual Channel specific status. BAR: Register: Offset: 3.3.6.11 DMIRCBAR DMIVC1RSTS 0026h Bit Attr Default 15:2 RO 0h Description Reserved. Reserved and Zero for future R/WC/S implementations. Software must use 0 for writes to these bits. 1 RO 1 Virtual Channel 1 Negotiation Pending (VC1NP): 0 = The VC negotiation is complete.
Processor Integrated I/O (IIO) Configuration Registers 3.3.6.12 DMILCTRL—DMI Link Control This register allows control of DMI. BAR: Register: Offset: Bit Attr Default 15:8 RO 0h 7 RW 0 6:2 RO 0h 1:0 3.3.6.13 DMIRCBAR DMILCTRL 0088h RW 00b Description Reserved Extended Synch (EXTSYNC) 0 = Standard Fast Training Sequence (FTS). 1 = Forces the transmission of additional ordered sets when exiting the L0s state and when in the Recovery state.
Processor Integrated I/O (IIO) Configuration Registers 3.4 Integrated I/O Core Registers (Device 8, Function 0-3) This section describes the standard PCI configuration registers and device specific Configuration Registers related to below: • • • • Intel VT-d, address mapping, system management — Device 8, Function 0 Semaphore and Scratchpad — Device 8, Function 1 System control/status — Device 8, Function 2 Miscellaneous Registers — Device 8, Function 3 3.4.
Processor Integrated I/O (IIO) Configuration Registers Table 3-8. Core Registers (Device 8, Function 0) — Offset 100h–1FFh Reserved for PCI Express header space 100h VTBAR 104h IIOBUSNO 180h VTGENCTRL 184h 108h VTISOCHCTRL 188h LMMIOL.LIMIT LMMIOL.BASE 10Ch VTGENCTRL2 18Ch LMMIOH.LIMIT LMMIOH.BASE 110h VTSTS 190h LMMIOH.BASEU 114h 194h LMMIOH.LIMITU 118h 198h 11Ch 19Ch 120h 1A0h LCFGBUS.L IMIT LCFGBUS.B ASE GMMIOL.LIMIT GMMIOL.BASE 124h 1A4h GMMIOH.LIMIT GMMIOH.
Processor Integrated I/O (IIO) Configuration Registers Table 3-9.
Processor Integrated I/O (IIO) Configuration Registers Table 3-10.
Processor Integrated I/O (IIO) Configuration Registers Table 3-11.
Processor Integrated I/O (IIO) Configuration Registers Table 3-12.
Processor Integrated I/O (IIO) Configuration Registers 3.4.2 Standard PCI Configuration Registers 3.4.2.1 VID—Vendor Identification Register Read only Vendor ID (Intel) value. Register: Device: Function: Offset: 3.4.2.2 Bit Attr Default 15:0 RO 8086h Description Vendor Identification Number (VID) PCI Standard Identification for Intel. DID—Device Identification Register Register: Device: Function: Offset: Bit 15:0 3.4.2.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 3) Register: Device: Function: Offset: Bit Attr Default Description 8 RO 0 SERR Enable For PCI Express/DMI ports, this field enables notifying the internal core error logic of occurrence of an uncorrectable error (fatal or non-fatal) at the port. The internal core error logic of Integrated I/O then decides if/how to escalate the error further (pins/message and so forth).
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 3) Register: Device: Function: Offset: Bit Attr Default Description 8 RO 0 SERR Enable For PCI Express/DMI ports, this field enables notifying the internal core error logic of occurrence of an uncorrectable error (fatal or non-fatal) at the port. The internal core error logic of Integrated I/O then decides if/how to escalate the error further (pins/message and so forth).
Processor Integrated I/O (IIO) Configuration Registers (Sheet 3 of 3) Register: Device: Function: Offset: Bit 0 3.4.2.4 PCICMD 8 0-3 04h Attr Default Description 0 IO Space Enable Applies only to PCI Express/DMI ports 0 = Disables the I/O address range, defined in the IOBASE and IOLIM registers of the PCI-to-PCI bridge header, for target decode from primary side.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Register: Device: Function: Offset: Bit 12 102 PCISTS 8 0-3 06h Attr RO Default Description 0 Received Target Abort This bit is set when a device experiences a completor abort condition on a transaction it mastered on the primary interface (Integrated I/O internal bus).
Processor Integrated I/O (IIO) Configuration Registers 3.4.2.5 RID—Revision Identification Register This register contains the revision number of the Integrated I/O. Register: Device: Function: Offset: RID 8 0-3 08h Bit Attr Default 7:4 RO See description Description Minor Revision Steppings which required all masks be regenerated. Refer to the Intel® Core™ i7-800 and i5-700 Desktop Processor Series Specification Update for the value of the Revision ID Register. 3:0 3.4.2.
Processor Integrated I/O (IIO) Configuration Registers 3.4.2.8 HDR—Header Type Register This register identifies the header layout of the configuration space. Register: Device: Function: Offset: 3.4.2.9 Bit Attr Default 7 RO 1b 6:0 RO 00h Multi-function Device This bit is set to 0 for Single Function Devices and 1 for multi- function devices. Configuration Layout This field identifies the format of the configuration header layout. Type1 for all PCI Express* ports and Type 0 for DMI devices.
Processor Integrated I/O (IIO) Configuration Registers 3.4.2.12 INTLIN—Interrupt Line Register The Interrupt Line register is used to communicate interrupt line routing information between initialization code and the device driver. Register: Device: Function: Offset: 3.4.2.13 INTLIN 8 0-2 3Ch Bit Attr Default 7:0 RO 00h Description Interrupt Line This bit is RW for devices that can generate a legacy INTx message and is needed only for compatibility purposes.
Processor Integrated I/O (IIO) Configuration Registers 3.4.3.2 NXTPTR—PCI Express® Next Capability List Register The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3.0 configuration space. Device: Function: Offset: 3.4.3.3 8 0, 1, 2 41h Bit Attr Default 7:0 RO 0 Description Next Ptr This field contains the offset to the next PCI Capability structure.
Processor Integrated I/O (IIO) Configuration Registers 3.4.3.4 DEVCAP—PCI Express® Device Capabilities Register The PCI Express Device Capabilities register identifies device specific information for the device. Device: Function: Offset: 8 0, 1, 2 44h Bit Attr Default Description 31:28 RO 0h Reserved 27:26 RO 0h Captured Slot Power Limit Scale Does not apply to root ports or integrated devices.
Processor Integrated I/O (IIO) Configuration Registers 3.4.3.5 DEVCTRL—PCI Express® Device Control Register The PCI Express Device Control register controls PCI Express specific capabilities parameters associated with the device. (Sheet 1 of 2) Device: Function: Offset: Bit Attr Default 15 RO 0h 14:12 RO 000 11 RO 0 Enable No Snoop Not applicable to root ports since they never set the ‘No Snoop’ bit for transactions they originate (not forwarded from peer) to PCI Express.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Device: Function: Offset: Bit 1 0 Datasheet, Volume 2 8 0, 1, 2 48h Attr RO RO Default Description 0 Non Fatal Error Reporting Enable This bit applies only to the PCI Express/DMI ports. The bit controls the reporting of non-fatal errors that IIO detects on the PCI Express/DMI interface or any non-fatal errors that PerfMon detect. 0 = Reporting of Non Fatal error detected by device is disabled.
Processor Integrated I/O (IIO) Configuration Registers 3.4.3.6 DEVSTS—PCI Express® Device Status Register The PCI Express Device Status register provides information about PCI Express device specific parameters associated with the device. Device: Function: Offset: Bit Attr Default 15:6 RO 000h Description Reserved Transactions Pending 0 = This bit cleared only when all Completions for any outstanding NonPosted Requests it owns have been received.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4 Intel® VT-d, Address Mapping, System Management Registers (Device 8, Function 0) 3.4.4.1 IIOMISCCTRL—Integrated I/O Misc Control Register Register: Device: Function: Offset: IIOMISCCTRL 8 0 98h Bit Attr Default 31:14 RV 0 Reserved 13 RW 0 CPUCSR_IB_Abort This bit controls if inbound access to CPUCSR range is enabled. 0 = IB access to CPUCSR range is disabled, that is, allowed.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.2 IIOMISCSS—Integrated I/O MISC Status This register can be used to read the status of Integrated I/O strapping pins. Register: Device: Function: Offset: Bit Attr Default Description 31:5 RO 0 Reserved 4 RO 1b Reserved 3 RO 1b Reserved 2:0 3.4.4.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.4 TOLM—Top of Low Memory Top of low memory. Note that bottom of low memory is assumed to be 0. Register: Device: Function: Offset: 3.4.4.5 TOLM 8 0 D0h Bit Attr Default Description 31:26 RWLB 0 TOLM Address Indicates the top of low DRAM memory which is aligned to a 64-MB boundary. A 32-bit transaction that satisfies ‘0 ≤ A[31:26] ≤ TOLM[31:26]” is a transaction towards main memory.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.7 NCMEM.LIMIT—NCMEM Limit Limit address of Intel QuickPath Interconnect non-coherent memory. Register: Device: Function: Offset: Bit 3.4.4.8 NCMEM.LIMIT 8 0 E4h Attr Default Description 63:26 RW 0 Non-Coherent Memory Limit Address Describes the limit address of a 64-MB aligned DRAM memory region on Intel QuickPath Interconnect that is non-coherent. Address bits [63:26] of an inbound address if it satisfies ‘NcMem.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 3) Register: Device: Function: Offset: Bit DEVHIDE1 8 0 F0h Attr Default Description Hide_Dev16_Fun0 When set, hide Device #16/Function #0 When set, all PCI configuration accesses from Intel QuickPath Interconnect targeting the corresponding device’s configuration space inside IIO are master aborted. When clear, configuration accesses targeting the device’s configuration space are allowed.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 3 of 3) Register: Device: Function: Offset: Bit Attr Default Description 3 RWL 0 Hide_Dev3 When set, hide Device 3 1. This bit has no impact on any configuration transactions that target the secondary side of a device that is a PCI-to-PCI bridge. 2. This bit has no effect on JTAG initiated accesses to corresponding device’s configuration space. 3.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.9 DEVHIDE2—Device Hide 2 Register This register provides a method to hide the PCI configuration space of devices inside IIO, from the host initiated configuration accesses. This register does not impact JTAG initiated accesses to the corresponding device’s configuration space.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.10 IIOBUSNO—IIO Internal Bus Number Register: Device: Function: Offset: Bit Attr Default 15:9 RV 00h 8 7:0 3.4.4.11 RW RW Description Reserved 0b Valid 0 = The IIO claims PCI configuration access to its internal devices (device/function) defined in Table 3-1, “Functions Handled by the Processor Integrated I/O (IIO)” with ANY Bus number, regardless of bits[7:0] of this register.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.12 LMMIOL.LIMIT—Local MMIOL Limit Register: Device: Function: Offset: Bit 3.4.4.13 Attr Default Description Local MMIOL Limit Address This field corresponds to A[31:24] of MMIOL limit. An inbound or outbound memory address that satisfies ‘local MMIOL base[15:8] ≤ A[31:24] ≤ local MMIOL limit[15:8]’ is treated as a local peer-to-peer transaction that does not cross an Intel QuickPath Interconnect link. Setting LMMIOL.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.15 LMMIOH.BASEU—Local MMIOH Base Upper Register: Device: Function: Offset: Bit Attr Default 31:19 RO 0000h 18:0 3.4.4.16 00000h This field corresponds to address A[63:51] of the local MMIOH range and is always 0. Local MMIOH Base Upper Address This field corresponds to A[50:32] of MMIOH base.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.18 LCFGBUS.LIMIT—Local Configuration Bus Number Limit Register Register: Device: Function: Offset: Bit 7:0 3.4.4.19 Attr RW Default Description 00h Local Configuration Bus Number Limit This field corresponds to Limit bus number of bus number range allocated to the hierarchy below the Intel QuickPath Interconnect link.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.21 GMMIOH.BASE—Global MMIOH Base Register: Device: Function: Offset: Bit 3.4.4.22 Attr Default Description Global MMIOH Base Address This field corresponds to A[31:26] of global MMIOH base.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.23 GMMIOH.BASEU—Global MMIOH Base Upper Register: Device: Function: Offset: Bit Attr Default 31:19 RO 0h This field corresponds to address A[63:51] of the global MMIOH range and is always 0. 0h Global MMIOH Base Upper Address This field corresponds to A[50:32] of global MMIOH base.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.26 GCFGBUS.LIMIT—Global Configuration Bus Number Limit Register Register: Device: Function: Offset: Bit 7:0 3.4.4.27 GCFGBUS.LIMIT 8 0 135h Attr RW Default Description FFh Global Configuration Bus Number Limit This field corresponds to limit bus number of bus number range allocated across all IIOs in the partition.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.29 VTBAR—Base Address Register for Intel® VT-d Chipset Registers Register: Device: Function: Offset: Bit VTBAR 8 0 180h Attr Default Description Intel VT-d Chipset Base Address This field provides an aligned 8-K base address for IIO registers relating to Intel VT-d. All inbound accesses to this region are completer aborted by the IIO. This is programmed once at boot time and does not change after that.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.30 VTGENCTRL—Intel® VT-d General Control Register Register: Device: Function: Offset: VTGENCTRL 8 0 184h Bit Attr Default 15 RWO 0b Lock Intel VT-d When this bit is 0, the VTBAR[0] is RWL (where the lock functionality is described in VTBAR register). When this bit is 0, VTBAR[0] is RO.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.31 VTISOCHCTRL—Intel VT-d Isoch Related Control Register Register: Device: Function: Offset: 3.4.4.
Processor Integrated I/O (IIO) Configuration Registers 3.4.4.33 VTSTS—Intel® VT-d Status Register Register: Device: Function: Offset: Bit VTSTS 8 0 190h Attr Default Description 31:2 RV 00000000h 1 RW1CS 0 Interrupt Transaction Seen on VC1/VCp 0 RW1CS 0 Reserved Reserved 3.4.5 Semaphore and ScratchPad Registers (Dev:8, F:1) 3.4.5.1 SR[0:3]—Scratch Pad Register 0-3 (Sticky) Register: Device: Function: Offset: 3.4.5.
Processor Integrated I/O (IIO) Configuration Registers 3.4.5.4 SR[12:15]—Scratch Pad Register 12-15 (Non-Sticky) Register: Device: Function: Offset: 3.4.5.5 Bit Attr Default 31:0 RWLB 0h Scratch Pad — Non-Sticky Non-sticky scratch pad registers for firmware utilization. SR[16:17] 8 1 0BCh-0C0h by 4 Bit Attr Default 31:0 RWLB 0h Description Scratch Pad — Non-Sticky Non-sticky scratch pad registers for firmware utilization.
Processor Integrated I/O (IIO) Configuration Registers 3.4.5.8 CWR[4:7]—Conditional Write Registers 4-7 Register: Device: Function: Offset: Bit 31:0 3.4.5.9 Attr RWSLB Bit 31:0 0h Description Conditional Write These registers are physically mapped to scratch pad registers. A read from CWR[n] reads SR[n]. A write to CWR[n] writes SR[n] if SR[n][0] = 0 before the write, and has no effect otherwise.
Processor Integrated I/O (IIO) Configuration Registers 3.4.5.11 CWR[16:17]—Conditional Write Registers 16-17 Register: Device: Function: Offset: Bit 31:0 3.4.5.12 Attr RWLB Default Description 0h Conditional Write These registers are physically mapped to scratch pad registers. A read from CWR[n] reads SR[n]. A write to CWR[n] writes SR[n] if SR[n][0] = 0 before the write, and has no effect otherwise.
Processor Integrated I/O (IIO) Configuration Registers 3.4.5.14 IR[4:7]—Increment Registers 4-7 Register: Device: Function: Offset: Bit 31:0 3.4.5.15 Attr RWSLB Bit 31:0 Description 0h Increment These registers are physically mapped to scratch pad registers. A read from IR[n] reads SR[n] and then increments SR[n]. A write to IR[n] increments SR[n] while the write data is unused. Increments within SR[n] for reads and writes roll over to zero.
Processor Integrated I/O (IIO) Configuration Registers 3.4.5.17 IR[16:17]—Increment Registers 16-17 Register: Device: Function: Offset: Bit 31:0 3.4.5.18 IR[16:17] 8 1 180h-184h by 4 Attr RWLB Default Description 0h Increment These registers are physically mapped to scratch pad registers. A read from IR[n] reads SR[n] and then increments SR[n]. A write to IR[n] increments SR[n] while the write data is unused. Increments within SR[n] for reads and writes roll over to zero.
Processor Integrated I/O (IIO) Configuration Registers 3.4.6 System Control/Status Registers (Device 8, Function 2) 3.4.6.1 SYSMAP—System Error Event Map Register This register maps the error severity detected by the IIO to one of the system events. Register: Device: Function: Offset: Bit Attr Default 31:7 RV 0 6:4 RWS 010 3 RV 0 2:0 3.4.6.
Processor Integrated I/O (IIO) Configuration Registers 3.4.6.3 SYRE—System Reset This register controls IIO (Integrated I/O) Reset behavior. Any resets produced by a write to this register must be delayed until the configuration write is completed on the initiating interface (PCI Express, DMI, JTAG). There is no “SOFT RESET” bit in this register. That function is invoked through the DMI interface. There are no Intel QuickPath Interconnect PCI Express gear ratio definitions in this register.
Processor Integrated I/O (IIO) Configuration Registers 3.4.7.2 IIOSLPSTS_H—IIO Sleep Status High Register Register: Device: Function: Offset: Bit Attr Default 31:12 RV 000h 11:0 3.4.7.3 ROS 0h Description Reserved SLPDUR_H: Sleep Duration High This is the upper 12 bits of the IIOSLPSTS register field that indicates the number of clocks that the IIO has been put to sleep. The IIO will clear this register on entry into sleep state and will increments it for every clock that the IIO is asleep.
Processor Integrated I/O (IIO) Configuration Registers 3.4.7.4 CTSTS—Throttling Status Register Register: Device: Function: Offset: 3.4.7.5 Bit Attr Default 7:2 RV 00h 1 RW1CS 0 Integrated I/O Throttling Event This bit is asserted when a high temperature situation is signalled from the processor uncore logic, and reset when de-asserted. 0 RV 0 Reserved Description Reserved CTCTRL—Throttling Control Register Register: Device: Function: Offset: 3.
Processor Integrated I/O (IIO) Configuration Registers 3.5.1 Intel® VT-d Configuration Register Space (MMIO) Table 3-13.
Processor Integrated I/O (IIO) Configuration Registers Table 3-14.
Processor Integrated I/O (IIO) Configuration Registers INVADDRREG IOTLBINV 140 200h 280h 204h 284h 208h 288h 20Ch 28Ch 210h 290h 214h 294h 218h 298h 21Ch 29Ch 220h 2A0h 224h 2A4h 228h 2A8h 22Ch 2ACh 230h 2B0h 234h 2B4h 238h 2B8h 23Ch 2BCh 240h 2C0h 244h 2C4h 248h 2C8h 24Ch 2CCh 250h 2D0h 254h 2D4h 258h 2D8h 25Ch 2DCh 260h 2E0h 264h 2E4h 268h 2E8h 26Ch 2ECh 270h 2F0h 274h 2F4h 278h 2F8h 27Ch 2FCh Datasheet, Volume 2
Processor Integrated I/O (IIO) Configuration Registers 3.5.2 Register Description In the following sections, Intel VT-d registers [0] correspond to the non-isochronous Intel VT-d remap engine and registers [1] correspond to the Isochronous Intel VT-d remap engine. 3.5.2.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.2 VTD_CAP[0:1]—Intel® VT-d Chipset Capabilities Register (Sheet 1 of 2) Register: Addr: BAR: Offset: Bit Attr Default 63:56 RV 0 Reserved 55:54 RO 11b Reserved 53:48 RO 09h Max Address Mask Value (MAMV) IIO supports MAMV value of 9h.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.3 EXT_VTD_CAP[0:1]—Extended Intel® VT-d Capability Register Register: Addr: BAR: Offset: EXT_VTD_CAP[0:1] MMIO VTBAR 10h, 1010h Bit Attr Default Description 63:24 RV 0 Reserved 23:20 RO Fh Max Handle Mask Value IIO supports all 16 bits of handle being masked. Note: IIO always performs global interrupt entry invalidation on any interrupt cache invalidation command and h/w never really looks at the mask value.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.4 GLBCMD[0:1]—Global Command Register Register: Addr: BAR: Offset: Bit Attr Default 31 RV 0 Reserved Description 30 RW 0 Set Root Table Pointer Software sets this field to set/update the root-entry table pointer used by hardware. The root-entry table pointer is specified through the Root-entry Table Address register.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.5 GLBSTS[0:1]—Global Status Register (Sheet 1 of 2) Register: Addr: BAR: Offset: 3.5.2.6 GLBSTS[0:1] MMIO VTBAR 1Ch, 101Ch Bit Attr Default 31 RO 0 Translation Enable Status When set, this bit indicates that translation hardware is enabled and when clear indicates the translation hardware is not enabled. 30 RO 0 Set Root Table Pointer Status This field indicates the status of the root- table pointer in hardware.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.7 CTXCMD[0:1]—Context Command Register Register: Addr: BAR: Offset: Bit 63 62:61 Attr RW RW Default Description 0 Invalidate Context Entry Cache (ICC) Software requests invalidation of context-cache by setting this field. Software must also set the requested invalidation granularity by programming the CIRG field. Software must read back and check the ICC field to be clear to confirm the invalidation is complete.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.8 FLTSTS[0:1]—Fault Status Register Register: Addr: BAR: Offset: FLTSTS[0:1] MMIO VTBAR 34h, 1034h Bit Attr Default 31:16 RV 0 Reserved Datasheet, Volume 2 Description 15:8 ROS 0 Fault Record Index This field is valid only when the Primary Fault Pending field is set.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.9 FLTEVTCTRL[0:1]—Fault Event Control Register Register: Addr: BAR: Offset: Bit 31 148 FLTEVTCTRL[0:1] MMIO VTBAR 38h, 1038h Attr RW Default Description 1 Interrupt Message Mask (IMM) 0 = Software has cleared this bit to indicate interrupt service is available.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.10 FLTEVTDATA[0:1]—Fault Event Data Register Register: Addr: BAR: Offset: Bit 3.5.2.11 Default Description RO 0 Reserved 15:0 RW 0 Interrupt Data FLTEVTADDR[0:1]—Fault Event Address Register FLTEVTADDR[0:1] MMIO VTBAR 40h, 1040h Bit Attr Default Description 31:2 RW 0 Interrupt Address The interrupt address is interpreted as the address of any other interrupt from a PCI Express port.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.14 PROT_LOW_MEM_BASE[0:1]—Protected Memory Low Base Register Register: Addr: BAR: Offset: Bit 3.5.2.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.17 PROT_HIGH_MEM_LIMIT[0:1]—Protected Memory Limit Base Register Register: Addr: BAR: Offset: Bit 3.5.2.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.20 INV_QUEUE_ADD[0:1]—Invalidation Queue Address Register Register: Addr: BAR: Offset: 3.5.2.21 Bit Attr Default 63:12 RW 0 IRQ Base This field points to the base of size-aligned invalidation request queue. 11:3 RV 0 Reserved 2:0 RW 0 Queue Size This field specifies the length of the invalidation request queue. The number of entries in the invalidation queue is defined as 2^(X + 8), where X is the value programmed in this field.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.22 INV_COMP_EVT_CTL[0:1]—Invalidation Completion Event Control Register Register: Addr: BAR: Offset: Bit 31 3.5.2.23 Attr RW Default Description 1 Interrupt Mask (IM) 0 = No masking of interrupt. When a invalidation event condition is detected, hardware issues an interrupt message (using the Invalidation Event Data & Invalidation Event Address register values). 1 = This is the value on reset.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.25 INV_COMP_EVT_UPRADDR[0:1]—Invalidation Completion Event Upper Address Register Register: Addr: BAR: Offset: 3.5.2.26 Bit Attr Default 31:0 RW 0 Description Address Integrated I/O (IIO) supports extended interrupt mode and implements this register.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.27 FLTREC[10,7:0]—Fault Record Register FLTREC[10] register is for the Isochronous Intel VT-d engine and [7:0] registers are for non-isochronous Intel VT-d engine. Register: Addr: BAR: Offset: Bit 3.5.2.28 FLTREC[10,7:0] MMIO VTBAR 1100h, 170h,160h,150h,140h,130h,120h,110h,100h Attr Default Description 127 RW1CS 0 Fault (F) Hardware sets this field to indicate a fault is logged in this fault recording register.
Processor Integrated I/O (IIO) Configuration Registers 3.5.2.29 IOTLBINV[0:1]—IOTLB Invalidate Register Register: Addr: BAR: Offset: Bit 63 62:60 156 IOTLBINV[0:1] MMIO VTBAR 208h, 1208h Attr RW RW Default Description 0 Invalidate IOTLB cache (IVT) Software requests IOTLB invalidation by setting this field. Software must also set the requested invalidation granularity by programming the IIRG field. Hardware clears the IVT field to indicate the invalidation request is complete.
Processor Integrated I/O (IIO) Configuration Registers 3.6 Intel® Trusted Execution Technology (Intel® TXT) Register Map Table 3-15. Intel® Trusted Execution Technology Registers TXT.STS TXT.ESTS TXT.THREADS.EXISTS TXT.THREADS.JOINS TXT.ERRORCODE TXT.Cmd.Res et TXT.Cmd.
Processor Integrated I/O (IIO) Configuration Registers Table 3-16. Intel® Trusted Execution Technology Registers, cont’d TXT.VER.QPIIF TXT.
Processor Integrated I/O (IIO) Configuration Registers Table 3-17. Intel® Trusted Execution Technology Registers, cont’d 200h 280h 204h 284h 208h 288h 20Ch 28Ch 210h 214h TXT.Cmd.Lock. Base TXT.Cmd.Unlo ck.Base TXT.SINIT.MEMORY.BASE TXT.SINIT.MEMORY.SIZE Datasheet, Volume 2 TXT.MLE.
Processor Integrated I/O (IIO) Configuration Registers Table 3-18. Intel® Trusted Execution Technology Registers, cont’d TXT.Heap.Base 300h TXT.Cmd.Ope n. Locality1 304h TXT.Heap.Size 308h 384h TXT.Cmd.Clos e. Locality1 30Ch TXT.MSEG.Base 310h TXT.Scratchpad0 TXT.Scratchpad1 160 318h 388h 38Ch TXT.Cmd.Ope n. Locality2 390h 394h 314h TXT.MSEG.Size 380h TXT.Cmd.Clos e.
Processor Integrated I/O (IIO) Configuration Registers Table 3-19. Intel® Trusted Execution Technology Registers, cont’d TXT.Public.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1 Intel® TXT Space Registers The Intel TXT registers adhere to the public and private attributes described in XREF. As described previously, each Intel TXT register may have up to three ways to access it. These are given the following symbolic names. TXT_TXT is the memory region starting at FED2_0000h when it is accessed using the special Intel TXT read or write commands.
Processor Integrated I/O (IIO) Configuration Registers (Sheet 2 of 2) Base: TXT_TXT Base: TXT_PR Base: TXT_PB Bit 14 RO Default Description 0 TXT.LOCALITY3.OPEN.STS This bit is set when the TXT.CMD.OPEN.LOCALITY3 command is seen by the chipset. It is cleared on reset or when TXT.CMD.CLOSE.LOCALITY3 is seen. This bit can be used by sw as a positive indication that the command has taken effect.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.2 TXT.ESTS—Intel® TXT Error Status Register This register is used to read the status associated with various errors that might be detected. General Behavioral Rules: • This register is available for read-only access from the Public configuration space. • This register is available for read and write access from the Private configuration space. Each status bit is cleared by writing to this register with a 1 in the corresponding bit position.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.3 TXT.THREADS.EXISTS—Intel® TXT Thread Exists Register This register is used to read which threads are registered as Intel TXT capable. General Behavioral Rules: • This is a read-only register, so writes to this register will be ignored. • This register is available in both the Public and Private Intel TXT configuration spaces. Base: TXT_TXT Offset: 0010h Base: TXT_PR Offset: 0010h Base: TXT_PB Offset: 0010h Bit 63:0 3.6.1.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.5 TXT.ERRORCODE—Intel® TXT Error Code Register When software discovers an error, it can write this scratch-pad register. However, the register is sticky and reset only by a power-good reset, and so allows diagnostic software (after the hard reset) to determine why the SENTER sequence failed (by examining various status bits). General Behavioral Rules: • This is a read-only register in the public Intel TXT configuration space.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.7 TXT.CMD.CLOSE_PRIVATE—Intel® TXT Close Private Command Register The processor that authenticates the SEXIT code does this to prevent the Intel TXT Private configuration space from being accessed using standard memory read/write cycles. General Behavioral Rules: • This is a write-only register. • This register is only available in the Private Intel TXT configuration space. • Accesses to this register are done with 1-byte writes.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.9 TXT.ID—Intel® TXT Identifier Register This register holds TXT ID for IIO. General Behavioral Rules: • This register is available in both the Public and Private Intel TXT configuration spaces. Base: TXT_TXT Base: TXT_PR Base: TXT_PB Bit 63:48 Attr RWLBS Offset: 0110h Offset: 0110h Offset: 0110h Default Description 0h TXT.ID.EXT This is an Extension onto the other ID fields.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.11 TXT.CMD.UNLOCK.BASE—Intel® TXT Unlock Base Command Register When this command is invoked, the chipset unlocks the registers listed in the table of registers and commands. When unlocked, the registers affected by this command may be written with public cycles, as well as private or Intel TXT cycles. General Behavioral Rules: • This is a write-only register. • This register is only available in the Private Intel TXT configuration space.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.13 TXT.SINIT.MEMORY.SIZE—Intel® TXT SINIT Memory Size Register This register indicates the size of the SINIT memory space. General Behavioral Rules: • This is a read/write register. • This register is available for read or write in the Private Intel TXT configuration space. Base: TXT_TXT Base: TXT_PR Base: TXT_PB 3.6.1.14 Offset: 0278h Offset: 0278h Offset: 0278h Bit Attr Default Description 63:0 RW 0h TXT.SINIT.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.15 TXT.HEAP.BASE—Intel® TXT HEAP Code Base Register This register holds a pointer to the base address for the Intel TXT Heap. General Behavioral Rules: • This is a read/write register. • This register is locked by TXT.CMD.LOCK.BASE. When locked this register is updated by private or Intel TXT writes, but not public writes • This register is available for read or write in the Public Intel TXT configuration space.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.17 TXT.MSEG.BASE—Intel® TXT MSEG Base Register This register holds a pointer to the base address for the TXT MSEG. General Behavioral Rules: • This is a read/write register. • This register is locked by TXT.CMD.LOCK.BASE. When locked it may not be changed by any writes, whether they are Intel TXT private or public writes. • This register is available for read or write in the Public Intel TXT configuration space.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.19 TXT.SCRATCHPAD0—Intel® TXT Scratch Pad Register 0 Intel TXT Scratch Pad Register. General Behavioral Rules: • This is a read/write register. • This register is locked by TXT.CMD.LOCK.BASE. When locked this register is updated by private or Intel TXT writes, but not public writes. • This register is available for read or write in the Public and Private Intel TXT configuration space.
Processor Integrated I/O (IIO) Configuration Registers 3.6.1.21 TXT.CMD.OPEN.LOCALITY1—Intel® TXT Open Locality 1 Command Enables Locality 1 decoding in chipset. General Behavioral Rules: • This is a write-only register. • This register is only available in the private Intel TXT configuration space. • Accesses to this register are done with 1-byte writes. • The data bits associated with this command are undefined and have no specific meaning. Base: TXT_TXT 3.6.1.
Processor Integrated I/O (IIO) Configuration Registers Note: PRIVATE space must also be Open for Locality 2 to be decoded as Intel TXT space. General Behavioral Rules: • This is a write-only register. • This register is only available in the private Intel TXT configuration space. • Accesses to this register are done with 1-byte writes. • The data bits associated with this command are undefined and have no specific meaning. Base: TXT_TXT Offset: 0390h Base: TXT_PR Offset: 0390h 3.6.1.
Processor Integrated I/O (IIO) Configuration Registers Intel® QuickPath Interconnect Device/Functions 3.7 The following device/functions control the Intel QuickPath Interconnect coherent link. Register Group Device Function Comment Intel QuickPath Interconnect Port 16 0 Link and PPR Intel QuickPath Interconnect Port 16 1 Routing and protocol Table 3-20.
Processor Integrated I/O (IIO) Configuration Registers 3.7.1 Intel® QuickPath Interconnect Link Layer Registers The link layer register are defined for the coherent link. There is a special attribute on some link layer registers to handle the link layer specific reset. The link layer only has hard and soft resets. ‘N’ attribute indicates that the register is reset on a link layer hard reset. ‘NN’ indicates that the register is reset on any link layer reset (hard or soft). 3.7.1.
Processor Integrated I/O (IIO) Configuration Registers 3.7.1.4 QPI[0]LCL—Intel® QuickPath Interconnect Link Control Register per Intel QuickPath Interconnect port. This register is used for Control of Link Layer. Register: Device: Function: Offset: 178 QPI[0]LCL 16 0 C4h Bit Attr Default Description 31:21 RO 0 Reserved 20 RWDS 0 L1 enable Bit is ANDed with the parameter exchanged value for L1 to determine if the link may enter L1.
Processor Integrated I/O (IIO) Configuration Registers 3.7.1.5 QPI[0]LCRDC—Intel® QuickPath Interconnect Link Credit Control Registers controls what credits are defined for each message class on VN0 and VNA. These credits are made visible on Intel QuickPath Interconnect during the initialization phase of the link layer. Incorrect programming can result in overflow of the receive queue.
Processor Integrated I/O (IIO) Configuration Registers Intel® QuickPath Interconnect Routing & Protocol Layer Registers 3.7.2 Table 3-21.
Processor Integrated I/O (IIO) Configuration Registers 3.7.2.1 QPIPCTRL0—Intel® QuickPath Interconnect Protocol Control 0 Register can only be modified under system quiescence. All RWL bits are locked with the lock1 bit. Register: Device: Function: Offset: Bit 31:30 3.7.2.2 QPIPCTRL0 16 1 4Ch Attr Default RWL Description 0 VC1 Priority When Isoc is enabled this value should is expected to be set as Critical.
Processor Integrated I/O (IIO) Configuration Registers Register: Device: Function: Offset: Bit 11:8 7:4 3:0 3.7.2.3 QPIPISOCRES 16 1 B8h Attr RW RW RW Default Description 0 VC1 Maximum Maximum tags that can be used for VC1 (Azalia) Traffic. Value should not be set greater then MaxRequests. It is required that “Pool Index” in QPI[0]PORB— QPI[0] Protocol Outgoing Request Buffer be disabled when Isoc traffic is enabled. When Isoc is enabled, this value must be set to >0.
Processor Uncore Configuration Registers 4 Processor Uncore Configuration Registers The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI specification as defined in the latest revision of the PCI Local Bus Specification, as well as the PCI Express* enhanced configuration mechanism as specified in the latest revision of the PCI Express Base Specification.
Processor Uncore Configuration Registers 4.2 Device Mapping Each component in the processor is uniquely identified by a PCI bus address consisting of Bus Number, Device Number and Function Number. Device configuration is based on the PCI Type 0 configuration conventions. All processor registers appear on the PCI bus assigned for the processor socket. Bus number is derived by the max bus range setting and processor socket number. Table 4-1.
Processor Uncore Configuration Registers 4.3 Detailed Configuration Space Maps Table 4-2.
Processor Uncore Configuration Registers Table 4-3.
Processor Uncore Configuration Registers Table 4-4.
Processor Uncore Configuration Registers Table 4-5.
Processor Uncore Configuration Registers Table 4-6.
Processor Uncore Configuration Registers Table 4-7.
Processor Uncore Configuration Registers Table 4-8.
Processor Uncore Configuration Registers Table 4-9.
Processor Uncore Configuration Registers Table 4-10.
Processor Uncore Configuration Registers Table 4-11.
Processor Uncore Configuration Registers Table 4-12.
Processor Uncore Configuration Registers Table 4-13.
Processor Uncore Configuration Registers Table 4-14.
Processor Uncore Configuration Registers Table 4-15.
Processor Uncore Configuration Registers Table 4-16.
Processor Uncore Configuration Registers Table 4-17.
Processor Uncore Configuration Registers 4.4 PCI Standard Registers These registers appear in every function for every device. 4.4.1 VID—Vendor Identification Register The VID Register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register uniquely identifies the manufacturer of the function within the processor. Writes to this register have no effect.
Processor Uncore Configuration Registers 4.4.3 RID—Revision Identification Register This register contains the revision number of the processor. The Revision ID (RID) is a traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI header of every PCI/PCI Express compatible device and function. Previously, a new value for RID was assigned for Intel chipsets for every stepping.
Processor Uncore Configuration Registers Device: 0 Function: 0, 1 Offset: 08h Device: 2 Function: 0, 1 Offset: 08h Device: 3 Function: 0, 1, 4 Offset: 08h Device: 4, 5 Function: 0–3 Offset: 08h Bit 7:4 3:0 Attr RO RO Default Description Minor Revision Steppings which required all masks be regenerated. See description Refer to the Intel® Core™ i7-800 and i5-700 Desktop Processor Series Specification Update for the value of the Revision ID Register.
Processor Uncore Configuration Registers 4.4.4 CCR—Class Code Register This register contains the Class Code for the device. Writes to this register have no effect. Device: 0 Function: 0, 1 Offset: 0Eh Device: 2 Function: 0, 1 Offset: 0Eh Device: 3 Function: 0, 1, 4 Offset: 0Eh Device: 4, 5 Function: 0–3 Offset: 0Eh Bit Default Description 23:16 RO 06h Base Class This field indicates the general device category. For the processor, this field is hardwired to 06h, indicating it is a “Bridge Device”.
Processor Uncore Configuration Registers 4.4.5 HDR—Header Type Register This register identifies the header layout of the configuration space. Device: 0 Function: 0, 1 Offset: 08h Device: 2 Function: 0, 1 Offset: 08h Device: 3 Function: 0, 1, 4 Offset: 08h Device: 4, 5 Function: 0–3 Offset: 08h Bit 7 6:0 4.4.6 Attr Default RO RO Description 1 Multi-Function Device This bit selects whether this is a multi-function device, that may have alternative configuration layouts.
Processor Uncore Configuration Registers 4.4.7 SID—Subsystem Identity This register identifies the system. It appears in every function. Device: 0 Function: 0, 1 Offset: 2Eh Device: 2 Function: 0, 1 Offset: 2Eh Device: 3 Function: 0, 1, 4 Offset: 2Eh Device: 4, 5 Function: 0–3 Offset: 2Eh 206 Bit Attr Default 15:0 RWO 8086h Description Subsystem Identification Number The default value specifies Intel.
Processor Uncore Configuration Registers 4.4.8 PCICMD—Command Register This register defines the PCI 3.0 compatible command register values applicable to PCI Express space. Device: 0 Function: 0, 1 Offset: 04h Device: 2 Function: 0, 1 Offset: 04h Device: 3 Function: 0, 1, 4 Offset: 04h Device: 4, 5 Function: 0–3 Offset: 04h Bit Attr Default 15:11 RV 0 Reserved.
Processor Uncore Configuration Registers 4.4.9 PCISTS—PCI Status Register The PCI Status register is a 16-bit status register that reports the occurrence of various error events on this device's PCI interface. Device: 0 Function: 0, 1 Offset: 06h Device: 2 Function: 0, 1 Offset: 06h Device: 3 Function: 0, 1, 4 Offset: 06h Device: 4, 5 Function: 0–3 Offset: 06h Bit Attr Default Description 15 RO 0 Detect Parity Error (DPE) The host bridge does not implement this bit and it is hardwired to a 0.
Processor Uncore Configuration Registers Device: 0 Function: 0, 1 Offset: 06h Device: 2 Function: 0, 1 Offset: 06h Device: 3 Function: 0, 1, 4 Offset: 06h Device: 4, 5 Function: 0–3 Offset: 06h Bit Attr Default 5 RO 0 66-MHz Capable Does not apply to PCI Express. Must be hardwired to 0. 1 Capability List (CLIST) This bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities.
Processor Uncore Configuration Registers Device: 0 Function: 1 Offset: 40h Access as a DWord 210 Bit Attr Default Description 27:26 RO 0 Reserved 25:24 RW 0 PAM3_LOENABLE. 0D0000h–0D3FFFh Attribute (LOENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh 00 = DRAM Disabled — All accesses are directed to DMI. 01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI. 10 = Write Only — All writes are send to DRAM.
Processor Uncore Configuration Registers 4.5.2 SAD_PAM456 Register for legacy device 0, function 0, 94h-97h address space. Device: 0 Function: 1 Offset: 44h Access as a DWord Bit Attr Default 31:22 RO 0 Reserved 0 PAM6_HIENABLE. 0EC000h–0EFFFFh Attribute (HIENABLE) This field controls the steering of read and write cycles that address the BIOS area from 0EC000h to 0EFFFFh. 00 = DRAM Disabled — All accesses are directed to DMI. 01 = Read Only — All reads are sent to DRAM.
Processor Uncore Configuration Registers 4.5.3 SAD_HEN Register for legacy Hole Enable. Device: 0 Function: 1 Offset: 48h Access as a DWord 4.5.4 Bit Attr Default Description 31:8 RO 0 Reserved 7 RW 0 HEN This field enables a memory hole in DRAM space. The DRAM that lies "behind" this space is not remapped. 0 = No Memory hole. 1 = Memory hole from 15 MB to 16 MB. 6:0 RO 0 Reserved SAD_SMRAM Register for legacy 9Dh address space.
Processor Uncore Configuration Registers 4.5.5 SAD_PCIEXBAR Global register for PCI ExpressXBAR address space. Device: 0 Function: 1 Offset: 50h Access as a QWord 4.5.6 Bit Attr Default Description 63:40 RV 0 Reserved 39:20 RW 0 ADDRESS Base address of PCI ExpressXBAR. Must be naturally aligned to size; low order bits are ignored. 19:4 RO 0 Reserved 3:1 RW 0 SIZE Size of the PCI ExpressXBAR address space. (MAX bus number).
Processor Uncore Configuration Registers 4.5.7 SAD_MCSEG_BASE Global register for McSEG address space. These are designed to look just like the cores SMRR type registers. Device: 0 Function: 1 Offset: 60h Access as a QWord 4.5.8 Bit Type Default Description 63:40 RV 0 Reserved 39:19 RW 0 BASE_ADDRESS Base address of McSEG. Must be 4K aligned (space must be power of 2 aligned). 18:0 RO 0 Reserved SAD_MCSEG_MASK Global register for McSEG address space.
Processor Uncore Configuration Registers 4.5.9 SAD_MESEG_BASE Register for Intel Management Engine (Intel ME) range base address. Device: 0 Function: 1 Offset: 70h Access as a QWord 4.5.10 Bit Attr Default Description 63:40 RV 0 Reserved 39:19 RW 0 BASE ADDRESS Base address of Intel ME SEG. Must be 4-K aligned (space must be power of 2 aligned). 18:0 RO 0 Reserved SAD_MESEG_MASK Register for Intel ME mask.
Processor Uncore Configuration Registers 4.5.11 SAD_DRAM_RULE_0; SAD_DRAM_RULE_2; SAD_DRAM_RULE_4; SAD_DRAM_RULE_6; SAD_DRAM_RULE_1 SAD_DRAM_RULE_3 SAD_DRAM_RULE_5 SAD_DRAM_RULE_7 SAD DRAM rules. Address Map for package determination. Device: 0 Function: 1 Offset: 80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch Access as a DWord 216 Bit Attr Default Description 31:20 RV 0 Reserved 19:6 RW - LIMIT.
Processor Uncore Configuration Registers 4.5.12 SAD_INTERLEAVE_LIST_0; SAD_INTERLEAVE_LIST_2; SAD_INTERLEAVE_LIST_4; SAD_INTERLEAVE_LIST_6; SAD_INTERLEAVE_LIST_1 SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_7 This register contains SAD DRAM package assignments. When the corresponding DRAM_RULE hits, a 3-bit number (determined by mode) is used to index into the interleave_list to determine which package is the HOME for this address.
Processor Uncore Configuration Registers 4.6 Intel® QuickPath Interconnect Link Registers 4.6.1 QPI_QPILCL_L0 Intel QuickPath Interconnect Link Control. Device: 2 Function: 0 Offset: 48h Access as a DWord Bit Type Default 31:22 RO 0 Reserved 0 L1_MASTER Indicates that this end of the link is the L1 master. This link transmitter bit is an L1 power state master and can initiate an L1 power state transition.
Processor Uncore Configuration Registers Device: 2 Function: 0 Offset: 48h Access as a DWord Bit 5:4 Datasheet, Volume 2 Type RWST Default Description 0 LLR_TO_LINK_RESET Consecutive LLRs to Link Reset — Sticky, Late action. 00 = up to 16 01 = up to 8 10 = up to 4 11 = 0, disable LLR (if CRC error, immediate error condition). 3:2 RWST 0 LINK_RESET_FROM_LLR Consecutive Link Reset from LLR till error condition (only applies if LLR enabled) — Sticky, Late action.
Processor Uncore Configuration Registers 4.7 Integrated Memory Controller Control Registers 4.7.1 MC_CONTROL Primary control register. Device: 3 Function: 0 Offset: 48h Access as a DWord Bit Attr Default 31:8 RO 0 Reserved 9 RW 0 CHANNEL1_ACTIVE When set, this bit indicates MC channel 1 is active. This bit is controlled (set/reset) by software only. This bit is required to be set for any active channel when INIT_DONE is set by software.
Processor Uncore Configuration Registers 4.7.2 MC_SMI_DIMM_ERROR_STATUS SMI DIMM error threshold overflow status register. This bit is set when the per-DIMM error counter exceeds the specified threshold. The bit is reset by BIOS. Device: 3 Function: 0 Offset: 50h Access as a DWord Bit Type Default 31:14 RO 0 Reserved 13:12 RW0C 0 REDUNDANCY_LOSS_FAILING_DIMM The ID for the failing DIMM when redundancy is lost. 11:8 7:0 4.7.
Processor Uncore Configuration Registers 4.7.4 MC_STATUS MC Primary Status register. Device: 3 Function: 0 Offset: 4Ch Access as a DWord Bit Attr Default 31:17 RO 0 Reserved 4 RO 1 Reserved 3 RO 0 Reserved 2 RO 0 Reserved 0 CHANNEL1_DISABLED. Channel 1 is disabled. This can be factory configured or if Init done is written without the channel_active being set. Clocks in the channel will be disabled when this bit is set. 0 CHANNEL0_DISABLED. Channel 0 is disabled.
Processor Uncore Configuration Registers 4.7.6 MC_CHANNEL_MAPPER Channel mapping register. The sequence of operations to update this register is: Read MC_Channel_Mapper register Compare data read to data to be written. If different then write. Poll MC_Channel_Mapper register until the data read matches data written. Device: 3 Function: 0 Offset: 60h Access as a DWord 4.7.
Processor Uncore Configuration Registers Device: 3 Function: 0 Offset: 64h Access as a DWord Bit 3:2 1:0 4.7.8 Attr RW RW Default Description 0 MAXNUMRANK. Maximum Number of Ranks 00 = Single Ranked 01 = Double Ranked 10 = Reserved 0 MAXNUMDIMMS. Maximum Number of DIMMs 00 = 1 DIMM 01 = 2 DIMMs 10 = Reserved 11 = Reserved MC_CFG_LOCK BIOS must write the MC_CFG_LOCK bit after configuration is complete to allow the Integrated Memory Controller to start accepting requests.
Processor Uncore Configuration Registers 4.7.9 MC_RD_CRDT_INIT These registers contain the initial read credits available for issuing memory reads. TAD read credit counters are loaded with the corresponding values at reset and anytime this register is written. BIOS must initialize this register with appropriate values depending on the level of Isoch support in the platform.
Processor Uncore Configuration Registers 4.7.10 MC_CRDT_WR_THLD Memory Controller Write Credit Thresholds. A Write threshold is defined as the number of credits reserved for this priority (or higher) request. It is required that High threshold be greater than or equal to Crit threshold, and that both be lower than the total Write Credit init value. BIOS must initialize this register with appropriate values depending on the level of Isoch support in the platform.
Processor Uncore Configuration Registers 4.8 TAD—Target Address Decoder Registers 4.8.1 TAD_DRAM_RULE_0; TAD_DRAM_RULE_2; TAD_DRAM_RULE_4; TAD_DRAM_RULE_6; TAD_DRAM_RULE_1 TAD_DRAM_RULE_3 TAD_DRAM_RULE_5 TAD_DRAM_RULE_7 TAD DRAM rules. Address map for channel determination within a package. All addresses sent to this HOME agent must hit a valid enabled DRAM_RULE. No error will be generated if they do not and memory aliasing will happen.
Processor Uncore Configuration Registers 4.8.2 TAD_INTERLEAVE_LIST_0; TAD_INTERLEAVE_LIST_2; TAD_INTERLEAVE_LIST_4; TAD_INTERLEAVE_LIST_6; TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_7 TAD DRAM package assignments. When the corresponding DRAM_RULE hits, a 3-bit number (determined by mode) is used to index into the Interleave_List Branches to determine which channel the DRAM request belongs to.
Processor Uncore Configuration Registers 4.9 Integrated Memory Controller Test Registers 4.9.1 Integrated Memory Controller Padscan Table 4-18.
Processor Uncore Configuration Registers The mask and halt bits are defined as shown in Table 4-20. Table 4-20. Halt and Mask Bit Usage Mask Halt Function 0 X Serial data is not loaded into the shadow register 1 0 Serial data is loaded into shadow register but will be overwritten 1 1 Serial data is loaded into shadow register and held until halt is cleared. This is the most commonly used setting. There are 3 registers defined for Padscan usage. Table 4-21.
Processor Uncore Configuration Registers A write operation is performed by writing the payload in the data register including mask and halt bits. The appropriate scan chain is selected in the scan chain select register. The index (offset +length of section –1) is written into the control register along with the write bit. The write is complete when the write bit is cleared. The write is complete when the write bit in the control register is cleared by the Integrated Memory Controller.
Processor Uncore Configuration Registers 4.9.3 MC_DIMM_CLK_RATIO Requested DIMM clock ratio (Qclk). This is the data rate going to the DIMM. The clock sent to the DIMM is 1/2 of QCLK rate. Device: 3 Function: 4 Offset: 54h Access as a DWord Bit Attr Default 31:5 RO 0 Reserved 6 QCLK_RATIO Requested ratio of Qclk/Bclk. 00000 = RSVD 00010 = 266 MHz 00100 = 533 MHz 00110 = 800 MHz 01000 = 1066 MHz 01010 = 1333 MHz 4:0 4.9.4 RW Description MC_TEST_LTRCON Memory test configuration register.
Processor Uncore Configuration Registers 4.9.5 MC_TEST_PH_CTR Memory test Control Register Device: 3 Function: 4 Offset: 6Ch Access as a DWord 4.9.
Processor Uncore Configuration Registers 4.9.7 MC_TEST_PAT_GCTR Pattern Generator Control. Device: 3 Function: 4 Offset: A8h Access as a DWord 234 Bit Attr Default Description 31:29 RO 0 Reserved 28:24 RW 6 EXP_LOOP_CNT Sets the length of the test, defined as 2^(EXP_LOOP_CNT). 23:22 RO 0 Reserved 21 RW 0 ERROR_COUNT_STALL Masks all detected errors until cleared. 20 RW1S 0 STOP_TEST Force exit from Loopback.Pattern. 19 RW 0 DRIVE_DC_ZERO Drive 0 on lanes with PAT_DCD asserted.
Processor Uncore Configuration Registers 4.9.8 MC_TEST_PAT_BA Memory Test Pattern Generator Buffer. Device: 3 Function: 4 Offset: B0h Access as a DWord 4.9.9 Bit Attr Default 31:0 RW 0 Description DATA 32-bit window into the indirectly-addressed pattern buffer register space. MC_TEST_PAT_IS Memory test pattern inversion selection register. Device: 3 Function: 4 Offset: BCh Access as a DWord 4.9.
Processor Uncore Configuration Registers 4.9.11 MC_TEST_EP_SCCTL Memory test electrical parameter scan chain control register. Device: 3 Function: 4 Offset: F8h Access as a DWord 4.9.12 Bit Attr Default Description 31 RW1S 0 SCAN_READ Perform a scan chain read. 30 RW1S 0 SCAN_WRITE Perform a san chain write. 29:16 RO 0 Reserved 15:0 RW 0 SCAN_OFFSET Shift count to perform upon next shift command. MC_TEST_EP_SCD Memory test electrical parameter scan chain data register.
Processor Uncore Configuration Registers 4.10 Integrated Memory Controller Channel Control Registers 4.10.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD Integrated Memory Controller DIMM reset command register. This register is used to sequence the reset signals to the DIMMs. Device: 4, 5 Function: 0 Offset: 50h Access as a DWord Bit Attr Default 31:3 RO 0 Reserved 2 RW 0 BLOCK_CKE When set, CKE will be forced to be deasserted.
Processor Uncore Configuration Registers 4.10.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD Integrated Memory Controller DIMM initialization command register. This register is used to sequence the channel through the physical layer training required for DDR. Device: 4, 5 Function: 0 Offset: 54h Access as a DWord Bit Attr Default 31:18 RO 0 Reserved 17 WO 0 ASSERT_CKE When set, all CKE will be asserted. Write a 0 to this bit to stop the init block from driving CKE.
Processor Uncore Configuration Registers 4.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS Initialization sequence parameters are stored in this register. Each field is 2^n count.
Processor Uncore Configuration Registers 4.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS The initialization state is stored in this register. This register is cleared on a new training command. Device: 4, 5 Function: 0 Offset: 5Ch Access as a DWord Bit Attr Default 31:10 RO 0 Reserved 9 RO 0 RCOMP_CMPLT When set, indicates that RCOMP command has complete. This bit is cleared by hardware on command issuance and set once the command is complete.
Processor Uncore Configuration Registers 4.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD DDR3 Configuration Command. This register is used to issue commands to the DIMMs such as MRS commands. The register is used by setting one of the *_VALID bits along with the appropriate address and destination RANK. The command is then issued directly to the DIMM. Care must be taken in using this register as there is no enforcement of timing parameters related to the action taken by a DDR3CMD write.
Processor Uncore Configuration Registers 4.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT This register supports Self Refresh and Thermal Throttle functions. Device: 4, 5 Function: 0 Offset: 68h Access as a DWord Bit Attr Default 31:4 RO 0 Reserved 0 INC_ENTERPWRDWN_RATE Powerdown rate will be increased during thermal throttling based on the following configurations.
Processor Uncore Configuration Registers 4.10.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2 The initial MRS register values for MR2. The RC fields do not need to be programmed if the address inversion and 3T/1T transitions are disabled. Device: 4, 5 Function: 0 Offset: 74h Access as a DWord Datasheet, Volume 2 Bit Attr Default Description 31:24 RO 0 Reserved 23:20 RW 0 Reserved 19:16 RW 0 Reserved 15:0 RW 0 MR2 The values to write to MR2 for A15:A0.
Processor Uncore Configuration Registers 4.10.9 MC_CHANNEL_0_RANK_PRESENT MC_CHANNEL_1_RANK_PRESENT This register provides the rank present vector. Device: 4, 5 Function: 0 Offset: 7Ch Access as a DWord Bit Attr Default 31:8 RO 0 Reserved 0 RANK_PRESENT Vector that represents the ranks that are present. Each bit represents a logical rank. When two or fewer DIMMs are present, [3:0] represents the four possible ranks in DIMM0 and [7:4] represents the ranks that are possible in DIMM1.
Processor Uncore Configuration Registers 4.10.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A This register contains parameters that specify the rank timing used. All parameters are in DCLK. Device: 4, 5 Function: 0 Offset: 80h Access as a DWord Bit Attr Default 31:27 RO 0 Reserved 0 tddWrTRd Minimum delay between a write followed by a read to different DIMMs.
Processor Uncore Configuration Registers Device: 4, 5 Function: 0 Offset: 80h Access as a DWord Bit 14:11 10:7 6:4 246 Attr RW RW RW Default Description 0 tdrRdTWr Minimum delay between Read followed by a write to different ranks on the same DIMM. 000 = 2 001 = 3 010 = 4 011 = 5 100 = 6 101 = 7 110 = 8 111 = 9 0 tsrRdTWr Minimum delay between Read followed by a write to the same rank.
Processor Uncore Configuration Registers 4.10.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B This register contains parameters that specify the rank timing used. All parameters are in DCLK. Device: 4, 5 Function: 0 Offset: 84h Access as a DWord Bit Attr Default 31:21 RO 0 Reserved 0 B2B_CAS_DELAY This field controls the delay between CAS commands in DCLKS. The minimum spacing is 4 DCLKS. Values below 3 have no effect. A value of 0 disables the logic.
Processor Uncore Configuration Registers 4.10.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING This register contains parameters that specify the bank timing parameters. These values are in DCLK. The values in these registers are encoded where noted. All of these values apply to commands to the same rank only. Device: 4, 5 Function: 0 Offset: 88h Access as a DWord 4.10.13 Bit Attr Default Description 31:22 RO 0 Reserved 21:17 RW 0 tWTPr: Minimum Write CAS to Precharge command delay.
Processor Uncore Configuration Registers 4.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING This register contains parameters that specify the CKE timings. All units are in DCLK. Device: 4, 5 Function: 0 Offset: 90h Access as a DWord Bit Datasheet, Volume 2 Attr Default Description 31:24 RW 0 tRANKIDLE Rank will go into powerdown after it has been idle for the specified number of DCLKs. tRANKIDLE covers max(txxxPDEN). Minimum value is tWRAPDEN.
Processor Uncore Configuration Registers 4.10.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING This register contains parameters that specify ZQ timing. All units are DCLK unless otherwise specified. The register encodings are specified where applicable. Device: 4, 5 Function: 0 Offset: 94h Access as a DWord Bit Attr Default 31 RO 0 Reserved 30 RW 1 Parallel_ZQ Enable ZQ calibration to different ranks in parallel. 29 RW 1 tZQenable Enable the issuing of periodic ZQCS calibration commands.
Processor Uncore Configuration Registers 4.10.17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1 This register contains parameters that specify ODT timings. All values are in DCLK. Device: 4, 5 Function: 0 Offset: 9Ch Access as a DWord Bit Attr Default 31:27 RO 0 Reserved 26:24 RW 0 TAOFD ODT turn off delay. 23:20 RW 6 MCODT_DURATION Controls the duration of MC ODT activation. BL/2 + 2. 19:16 RW 4 MCODT_DELAY Controls the delay from Rd CAS to MC ODT activation. This value is tCAS–1.
Processor Uncore Configuration Registers 4.10.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2 This register contains parameters that specify Forcing ODT on Specific ranks. Device: 4, 5 Function: 0 Offset: A0h Access as a DWord Bit 4.10.19 Attr Default Description 31:10 RO 0 Reserved 9 RW 0 MCODT_Writes. Drive MC ODT on reads and writes. 8 RW 0 FORCE_MCODT. Force MC ODT to always be asserted. 7 RW 0 FORCE_ODT7. Force ODT for Rank 7 to always be asserted. 6 RW 0 FORCE_ODT6.
Processor Uncore Configuration Registers 4.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD This register contains the ODT activation matrix for RANKS 4 to 7 for Reads. Device: 4, 5 Function:)0 Offset: A8h Access as a DWord 4.10.21 Bit Attr Default Description 31:24 RW 1 ODT_RD3. ODT values for all 8 Ranks when reading Rank 7. 23:16 RW 1 ODT_RD2. ODT values for all 8 Ranks when reading Rank 6. 15:8 RW 4 ODT_RD1. ODT values for all 8 Ranks when reading Rank 5.
Processor Uncore Configuration Registers 4.10.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS This register contains parameters that specify settings for the Write Address Queue. Device: 4, 5 Function: 0 Offset: B4h Access as a DWord 254 Bit Attr Default Description 31:30 RO 0 Reserved 29:25 RW 6 PRECASWRTHRESHOLD Threshold above which Medium-Low Priority reads cannot PRE-CAS write requests.
Processor Uncore Configuration Registers 4.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS These are the parameters used to control parameters within the scheduler. Device: 4, 5 Function: 0 Offset: B8h Access as a DWord 4.10.25 Bit Attr Default Description 31:14 RO 0 Reserved 13 RW 0 DDR_CLK_TRISTATE_DISABLE. When set to 0, DDR clock drivers will always be enabled. 12 RW 0 CS_ODT_TRISTATE_DISABLE. When set to 0, CS and ODT drivers will always be enabled.
Processor Uncore Configuration Registers 4.10.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS These are the parameters used to set the Start Scheduler for TX clock crossing. This is used to send commands to the DIMMs.
Processor Uncore Configuration Registers 4.10.27 MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS These are the parameters used to set the Rx clock crossing BGF. Device: 4, 5 Function: 0 Offset: C8h Access as a DWord 4.10.28 Bit Attr Default Description 31:27 RO 0 Reserved 26:24 RW 2 PTRSEP RX FIFO pointer separation settings. THIS FIELD IS NOT USED BY HARDWARE. RX Pointer separation can be modified using the round trip setting (larger value causes a larger pointer separation).
Processor Uncore Configuration Registers 4.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS These are the parameters to set the early warning RX clock crossing BGF. Device: 4, 5 Function: 0 Offset: D0h Access as a DWord 4.10.30 Bit Attr Default Description 31:16 RO 0 Reserved 15:8 RW 2 EVENOFFSET Early warning even offset setting. 7:0 RW 0 ODDOFFSET Early warning odd offset setting.
Processor Uncore Configuration Registers 4.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1 These are the parameters used to control parameters for page closing policies. Device: 4, 5 Function: 0 Offset: D8h Access as a DWord Bit Attr Default 31:16 RO 0 Reserved 15:8 RW 0 REQUESTCOUNTER Upper 8 MSBs of a 12-bit counter. This counter determines the window over which the page close policy is evaluated. 0 ADAPTIVETIMEOUTCOUNTER Upper 8 MSBs of a 12-bit counter.
Processor Uncore Configuration Registers 4.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1 Channel Bubble Generator ratios for CMD and DATA. Device: 4, 5 Function: 0 Offset: E0h Access as a DWord Bit 4.10.34 Attr Default Description 31:16 RO 0 Reserved 15:8 RW 0 ALIENRATIO. DCLK to BCLK ratio. 7:0 RW 0 NATIVERATIO. UCLK to BCLK ratio.
Processor Uncore Configuration Registers 4.11 Integrated Memory Controller Channel Address Registers 4.11.1 MC_DOD_CH0_0 MC_DOD_CH0_1 Channel 0 DIMM Organization Descriptor Register. Device: 4 Function: 1 Offset: 48h, 4Ch, 50h, 54h Access as a DWord Bit Attr Default Description 31:13 RO 0 Reserved 12:10 RW 0 RANKOFFSET Rank Offset for calculating RANK. This corresponds to the first logical rank on the DIMM. The rank offset is always programmed to 0 for the DIMM 0 DOD registers.
Processor Uncore Configuration Registers 4.11.2 MC_DOD_CH1_0 MC_DOD_CH1_1 Channel 1 DIMM Organization Descriptor Register. Device: 5 Function: 1 Offset: 48h, 4Ch, 50h, 54h Access as a DWord Bit Attr Default 31:13 RO 0 Reserved 12:10 RW 0 RANKOFFSET Rank Offset for calculating RANK. This corresponds to the first logical rank on the DIMM. The rank offset is always programmed to 0 for the DIMM 0 DOD registers. (DIMM 0 rank offset is always 0.) DIMM 1 DOD rank offset is 4 for two DIMMs per channel.
Processor Uncore Configuration Registers 4.11.3 MC_SAG_CH0_0; MC_SAG_CH0_1; MC_SAG_CH0_2; MC_SAG_CH0_3; MC_SAG_CH0_4; MC_SAG_CH0_5; MC_SAG_CH0_6; MC_SAG_CH0_7 Channel Segment Address Registers. For each of the 8 interleave ranges, they specify the offset between the System Address and the Memory Address and the System Address bits used for level 1 interleave, which should not be translated to Memory Address bits.
Processor Uncore Configuration Registers 4.11.4 MC_SAG_CH1_0; MC_SAG_CH1_1; MC_SAG_CH1_2; MC_SAG_CH1_3; MC_SAG_CH1_4; MC_SAG_CH1_5; MC_SAG_CH1_6; MC_SAG_CH1_7 Channel Segment Address Registers. For each of the 8 interleave ranges, they specify the offset between the System Address and the Memory Address and the System Address bits used for level 1 interleave, which should not be translated to Memory Address bits.
Processor Uncore Configuration Registers 4.12 Integrated Memory Controller Channel Rank Registers 4.12.1 MC_RIR_LIMIT_CH0_0; MC_RIR_LIMIT_CH0_2; MC_RIR_LIMIT_CH0_4; MC_RIR_LIMIT_CH0_6; MC_RIR_LIMIT_CH0_1; MC_RIR_LIMIT_CH0_3; MC_RIR_LIMIT_CH0_5; MC_RIR_LIMIT_CH0_7 Channel 0 Rank Limit Range Registers.
Processor Uncore Configuration Registers 4.12.
Processor Uncore Configuration Registers 4.12.
Processor Uncore Configuration Registers 4.13 Memory Thermal Control 4.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 Controls for the Integrated Memory Controller thermal throttle logic. Device: 4, 5 Function: 3 Offset: 48h Access as a DWord Bit Attr Default 31:3 RO 0 Reserved 2 RW 1 APPLY_SAFE Enable the application of safe values while MC_THERMAL_PARAMS_B.SAFE_INTERVAL is exceeded. 0 THROTTLE_MODE Selects throttling mode.
Processor Uncore Configuration Registers 4.13.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1 Thermal Throttle defeature register. Device: 4, 5 Function: 3 Offset: 50h Access as a DWord 4.13.4 Bit Attr Default Description 31:1 RO 0 Reserved 0 RW1S 0 THERM_REG_LOCK When set to 1, no further modification of all thermal throttle registers are allowed. This bit must be set to the same value for all channels.
Processor Uncore Configuration Registers 4.13.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1 Parameters used by the thermal throttling logic. Device: 4, 5 Function: 3 Offset: 64h Access as a DWord Bit 4.13.6 Attr Default Description 31:26 RW 1 SAFE_INTERVAL Safe values for cooling coefficient and duty cycle will be applied while the SAFE_INTERVAL is exceeded. This interval is the number of ZQ intervals since the last time the MC_COOLING_COEF or MC_CLOSED_LOOP registers have been written.
Processor Uncore Configuration Registers 4.13.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1 This register controls the closed loop thermal response of the DRAM thermal throttle logic. It supports immediate thermal throttle and 2X refresh. In addition, the register is used to configure the throttling duty cycle. Device: 4, 5 Function: 3 Offset: 84h Access as a DWord 4.13.
Processor Uncore Configuration Registers 4.13.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1 This register contains the 8 most significant bits [37:30] of the virtual temperature of each rank. The difference between the virtual temperature and the sensor temperature can be used to determine how fast fan speed should be increased. The value stored is right shifted one bit to the right with respect to the corresponding MC_Throttle_Offset register value.
Processor Uncore Configuration Registers 4.13.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1 This register contains the status portion of the DDR_THERM# functionality as described in the processor datasheet (that is, what is happening or has happened with respect to the pin). Device: 4, 5 Function: 3 Offset: A4h Access as a DWord Bit Attr Default 31:3 RO 0 Reserved 2 RO 0 ASSERTION An assertion edge was seen on DDR_THERM#. Write-1-to-clear.
Processor Uncore Configuration Registers 274 Datasheet, Volume 2
System Address Map 5 System Address Map 5.1 Introduction This chapter provides a basic overview of the system address map and describes how the processor IIO comprehends and decodes the various regions in the system address map. The term “IIO” in this chapter refers to processor IIO (in both End Point and Dual IIO Proxy modes). This chapter does not provide the full details of the platform system address space as viewed by software and also it does not provide the details of processor address decoding.
System Address Map The processor supports PCI Express* upper pre-fetchable base/limit registers. This allows the PCI Express unit to claim IO accesses above 36 bits, complying with the PCI Express Spec. Addressing of greater than 8 GB is allowed on either the DMI Interface or PCI Express interface. The memory controller supports a maximum of 8 GB of DRAM. No DRAM memory will be accessible above 8 GB. When running in internal graphics mode, writes to GMADR range linear range are supported.
System Address Map 5.2.1 System Address Map Figure 5-1. System address Map Privileged CSR (Not Used) TOCM 2^51 2^46 2^40 variable Reserved MMIOH variable (relocatable) TOHM TOCM DRAM High 2^40 N X 64 MB Memory 1_0000_0000 High Memory FF00_0000 FEF0_0000 4 GB FEE0_0000 FED0_0000 FEC0_0000 FEB0_0000 Low Memory FWH 16MB IntA/Rsvd 1MB LocalxAPIC 1MB LegacyLT/TPM 1MB I/OxAPIC 1MB LocalCSR/CPUOndirROM/Pseg 1MB Misc (CPEI, etc.
System Address Map 5.2.2 System DRAM Memory Regions Address Region From To 640-KB MS-DOS* Memory 000_0000_0000h 000_0009_FFFFh 1 MB to Top-of-Low-Memory 000_0010_0000h TOLM Bottom-of-High-Memory to Top-ofHigh-Memory 4 GB TOHM These address ranges are always mapped to system DRAM memory, regardless of the system configuration. The top of main memory below 4 GB is defined by the Top of Low Memory (TOLM). Memory between 4 GB and TOHM is extended system memory.
System Address Map 5.2.3 VGA/SMM and Legacy C/D/E/F Regions Figure 5-2 shows the memory address regions below 1 MB. These regions are legacy access ranges. Figure 5-2. VGA/SMM and Legacy C/D/E/F Regions 1MB VGA/SMM Regions 0C0000h 768 KB 0B8000h 736 KB 0B0000h 704 KB 0A0000h 640 KB BIOS, Shadow RAM accesses Controlled at 16K granularity in C P U Source decoder Controlled by VGA Enable and SMM Enable in CPU Key = VGA/SMM = Low BIOS = System Memory (DOS) 5.2.3.
System Address Map The VGA memory address range can also be mapped to system memory in SMM. IIO is totally transparent to the workings of this region in the SMM mode. All outbound and inbound accesses to this address range are always forwarded to the VGA device by the IIO. Refer to Table 5-7 and Table 5-8 for further details of inbound and outbound VGA decoding. 5.2.3.
System Address Map 5.2.4.1 Relocatable TSEG Address Region From To TSEG FE00_0000h (default) FE7F_FFFFh (default) These are system DRAM memory regions that are used for SMM/CMM mode operation. IIO would completer abort all inbound transactions that target these address ranges.
System Address Map 5.2.5.2 MMIOL Address Region From To MMIOL GMMIOL.Base GMMIOL.Limit This region is used for PCIe device memory addressing below 4 GB. Each IIO in the system is allocated a portion of this address range and individual PCIe ports and other integrated devices within an IIO (for example, VTBAR) use sub-portions within that range. There are IIO-specific requirements on how software allocates this system region amongst IIOs to support of peer-to-peer between IIOs. Refer to Section 5.8.
System Address Map 5.2.5.6 Local XAPIC Address Region From To Local XAPIC FEE0_0000h FEEF_FFFFh The processor Interrupt space is the address used to deliver interrupts to the processor(s). Message Signaled Interrupts (MSI) from PCIe devices that target this address are forwarded as SpcInt messages to the processor. The processors may also use this region to send inter-processor interrupts (IPI) from one processor to another. But, IIO is never a recipient of such an interrupt.
System Address Map 5.2.6 Address Regions above 4 GB 5.2.6.1 High System Memory Address Region From To High System Memory 4 GB TOHM This region is used to describe the address range of system memory above the 4-GB boundary. IIO forwards all inbound accesses to this region to the system memory port (unless any of these access addresses are also marked protected.). A portion of the address range within this high system DRAM region could be marked non-coherent (using NcMem.Base/NcMem.
System Address Map 5.2.6.3 BIOS Notes on Address Allocation above 4 GB The processor does not support hot added memory. Hence, no special BIOS actions are required for address allocation above 4 GB to maintain a hole. Since IIO supports only a single contiguous address range for accesses to system DRAM above 4 GB, BIOS must make sure that there is enough reserved space gap left between the top of high memory and the bottom of the MMIOH region, if the system cares about memory hot add.
System Address Map 5.3.2 ISA Addresses IIO supports ISA addressing per the PCI-PCI Bridge 1.2 Specification. ISA addressing is enabled in a PCIe port using the ISAEN bit in the bridge configuration space. Note that when VGAEN bit is set in a PCIe port without the VGA16DECEN bit being set, the ISAEN bit must be set in all the peer PCIe ports in the system. 5.3.3 CFC/CF8 Addresses These addresses are used by legacy operating systems to generate PCI configuration cycles.
System Address Map remote peer-to-peer. Refer to section Section 5.8.1 and Section 5.8.2 for details of how these registers are used in the inbound and outbound memory/configuration/message decoding. Configuration transactions initiated by the processor on Intel QuickPath Interconnect can have non-zero value for address bits 28 and above. This is an artifact of the uncore logic in the processor. IIO’s outbound configuration address decoder must ignore these bits when decoding the PCIe configuration space.
System Address Map 5.5.2 SMM Space Restrictions If any of the following conditions are violated the results of SMM accesses are unpredictable and may cause the system to hang: 1. The Compatible SMM space must not be set-up as cacheable. 2. High or TSEG SMM transaction address space must not overlap address space assigned to system DRAM, or to any “PCI” devices (including DMI Interface, and PCI Express, and graphics devices). This is a BIOS responsibility. 3.
System Address Map 5.5.4 SMM Control Combinations The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows software to write to the SMM ranges without being in SMM mode. BIOS software can use this bit to initialize SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM mode accesses. The D_CLS bit causes SMM (both CSEG and TSEG) data accesses to be forwarded to the DMI Interface or PCI Express.
System Address Map PCI Express and DMI Interface read accesses to the GMADR range are not supported therefore will have no address translation concerns. PCI Express and DMI Interface reads to GMADR will be remapped to address 000C_0000h. The read will complete with UR (unsupported request) completion status. GTT Fetches are always decoded (at fetch time) to ensure not in SMM (actually, anything above base of TSEG or 640 KB – 1 MB).
System Address Map 5.8 IIO Address Decoding In general, software needs to guarantee that for a given address there can only be a single target in the system. Otherwise, it is a programming error and results are undefined. The one exception is that VGA addresses would fall within the inbound coarse decode memory range. The IIO inbound address decoder handles this conflict and forwards the VGA addresses to only the VGA port in the system (and not system memory). 5.8.
System Address Map bit. There is no decode enable bit for configuration cycle decoding towards either a PCIe port or the internal CSR configuration space of IIO. • The target decoding for internal VTdCSR space is based on whether the incoming CSR address is within the VTdCSR range (limit is 8K plus the base, VTBAR).
System Address Map 5.8.1.4 Summary of Outbound Target Decoder Entries Table 5-4 provides a list of all the target decoder entries in IIO, such as PCIe port, required by the outbound target decoder to positively decode towards a target. Table 5-4. Outbound Target Decoder Entries Address Region Target Decoder Entry Comments VGA (Memory space A_0000h– B_FFFFh and I/O space 3B0h– 3BBh and 3C0h–3DFh) 4+11 Fixed. TPM/TXT/FW ranges (E/F segs and 4 G–16 M to 4 G) 1 Fixed. MMIOL 4 Variable.
System Address Map Table 5-6 details IIO behavior for configuration requests from Intel QuickPath Interconnect and peer-to-peer completions from Intel QuickPath Interconnect. Table 5-6.
System Address Map 5.8.2 Inbound Address Decoding This section covers the decoding that is done on any transaction that is received on a PCIe or DMI. 5.8.2.1 Overview • All inbound addresses that fall above the top of Intel QuickPath Interconnect physical address limit are flagged as errors by IIO. Top of Intel QuickPath Interconnect physical address limit is dependent on the Intel QuickPath Interconnect profile. • Inbound decoding towards main memory in IIO happens in two steps.
System Address Map 5.8.2.2 Summary of Inbound Address Decoding Table 5-8 summarizes IIO behavior on inbound memory transactions from any PCIe port. Note that this table is only intended to show the routing of transactions based on the address and is not intended to show the details of several control bits that govern forwarding of memory requests from a given PCI Express port. Refer to the PCI Express Base Specification 2.0 and the registers chapter for details of these control bits. Table 5-8.
System Address Map Table 5-8. Inbound Memory Address Decoding (Sheet 2 of 2) Address Range Other Peer-to-Peer4 Conditions Address within LMMIOL.BASE/LMMIOL.LIMIT or LMMIOH.BASE/LMMIOH.LIMIT and a PCIe port positively decoded as target Forward to the PCI Express port Address within LMMIOL.BASE/LMMIOL.LIMIT or LMMIOH.BASE/LMMIOH.LIMIT and no PCIe port positively decoded as target Forward to DMI Address NOT within LMMIOL.BASE/LMMIOL.LIMIT or LMMIOH.BASE/LIOH.LIMIT, but is within GMMIOL.BASE/GMMIOL.
System Address Map Table 5-9 summarizes IIO behavior on inbound I/O transactions from any PCIe port. Table 5-9.
System Address Map Table 5-10 summarizes IIO behavior on inbound configuration transactions from any PCIe port. Table 5-10.
System Address Map 5.8.3 Intel® VT-d Address Map Implications Intel VT-d applies only to inbound memory transactions. Inbound I/O and configuration transactions are not affected by Intel VT-d. Inbound I/O, configuration and message decode and forwarding happens the same whether Intel VT-d is enabled or not.