Datasheet

Datasheet 61
Package Mechanical Specifications and Pin Information
FERR#/PBE# Output
FERR# (Floating-point Error)/PBE# (Pending Break Event) is a
multiplexed signal and its meaning is qualified with STPCLK#.
When STPCLK# is not asserted, FERR#/PBE# indicates a floating
point when the processor detects an unmasked floating-point error.
FERR# is similar to the ERROR# signal on the Intel® 387
coprocessor, and is included for compatibility with systems using
Microsoft MS-DOS*-type floating-point error reporting. When
STPCLK# is asserted, an assertion of FERR#/PBE# indicates that
the processor has a pending break event waiting for service. The
assertion of FERR#/PBE# indicates that the processor should be
returned to the Normal state. When FERR#/PBE# is asserted,
indicating a break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is active will also
cause an FERR# break event.
For additional information on the pending break event functionality,
including identification of support of the feature and enable/disable
information, refer to Volumes 3A and 3B of the Intel® 64 and IA-
32 Architectures Software Developer's Manuals and the Intel®
Processor Identification and CPUID Instruction application note.
GTLREF Input
GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 V
CCP
. GTLREF is used by the AGTL+
receivers to determine if a signal is a logical 0 or logical 1.
Refer to the appropriate platform design guide for details on
GTLREF implementation.
GTLREF_2 Input
GTL reference level for AGTL+ input pins of the second die.
Refer to the appropriate platform design guide for details on
GTLREF implementation.
GTLREF_CONT
ROL
Input/
Output
This pin can be used as GTLREF_2 disconnect circuit control signal.
GTLREF_2 maps out to a reserved pin on Intel® Core
TM
2 Duo
Processor, for Dual Core and quad-core interchangeable
motherboard, GTLREF_CONTROL can be used as a control signal
for a circuit that will automaticlly switch between Dual Core and
quad-core modes.
HIT#
HITM#
Input/
Output
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Either FSB agent may assert both HIT#
and HITM# together to indicate that it requires a snoop stall that
can be continued by reasserting HIT# and HITM# together.
IERR# Output
IERR# (Internal Error) is asserted by the processor as the result of
an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#, BINIT#, or INIT#.
Table 14. Signal Description (Sheet 5 of 9)
Name Type Description