Datasheet

4 Datasheet
Figures
1 Core Low Power States..............................................................................................12
2 Package Low Power States.........................................................................................13
3 PSI-2 Functionality Logic Diagram ..............................................................................19
4 Active VCC and ICC Loadline for Quad-Core Extreme Mobile Processor.............................33
5 Deeper Sleep VCC and ICC Loadline for Quad-Core Extreme Mobile Processor...................34
6 Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 1 of 2) ................................38
7 Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 2 of 2) ................................39
8 Quad-Core Processor Pinout (Top Package View, Left Side) ............................................40
9 Quad-Core Processor Pinout (Top Package View, Right Side) ..........................................41
Tables
1 References ............................................................................................................... 9
2 Coordination of Core Low Power States at the Package Level..........................................13
3 Voltage Identification Definition..................................................................................23
4 BSEL[2:0] Encoding for BCLK Frequency......................................................................27
5 FSB Pin Groups ........................................................................................................28
6 Processor Absolute Maximum Ratings..........................................................................29
7 Voltage and Current Specifications for the Quad-Core Extreme Mobile Processors..............30
8 Voltage and Current Specifications for the Quad-Core Mobile Processors ..........................31
9 AGTL+ Signal Group DC Specifications ........................................................................34
10 CMOS Signal Group DC Specifications..........................................................................36
11 Open Drain Signal Group DC Specifications ..................................................................36
12 Pin Listing by Pin Name.............................................................................................42
13 Pin Listing by Pin Number..........................................................................................49
14 Signal Description.....................................................................................................57
15 New Pins for the Quad-Core Mobile Processor...............................................................66
16 Processor Power Specifications...................................................................................67
17 Thermal Diode Interface............................................................................................69
18 Thermal Diode Parameters Using Transistor Model ........................................................69