Intel® Core™2 Extreme Quad-Core Mobile Processor and Intel® Core™2 Quad Mobile Processor on 45-nm Process Datasheet For platforms based on Mobile Intel® 4 Series Express Chipset Family January 2009 Document Number: 320390-002
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Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 7 1.2 References ......................................................................................................... 9 2 Low Power Features ................................................................................................ 11 2.
Figures 1 2 3 4 5 6 7 8 9 Core Low Power States..............................................................................................12 Package Low Power States.........................................................................................13 PSI-2 Functionality Logic Diagram ..............................................................................19 Active VCC and ICC Loadline for Quad-Core Extreme Mobile Processor.............................
Revision History Document Number Revision Number 320390 -001 320390 -002 Description Initial Release • • Date August 2008 Updated Table 8: Added Q9000 information Updated Table 16: Added Q9000 information January 2009 § Datasheet 5
Datasheet
Introduction 1 Introduction The Intel® CoreTM2 Extreme quad-core processor and Intel® CoreTM2 quad processor on 45-nanometer process technology for platforms based on Mobile Intel® 4 Series Express Chipset Family is the first low-power, mobile quad-core processor based on the Intel® Core™ microarchitecture.
Introduction Term 8 Definition Storage Conditions Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1.
Introduction 10 Datasheet
Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The processor supports low power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states.
Low Power Features Figure 1.
Low Power Features Figure 2. Package Low Power States STPCLK# asserted SLP# asserted Stop Grant Normal DPSLP# asserted SLP# desserted STPCLK# desserted Snoop serviced DPRSTP# asserted Deep Sleep Sleep DPSLP# deasserted Deeper Sleep DPRSTP# desserted Snoop occurs Stop Grant Snoop Table 2.
Low Power Features While in AutoHALT Powerdown state, the due core processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the AutoHALT Powerdown state. 2.1.1.3 Core C1/MWAIT Powerdown State C1/MWAIT is a low power state entered when the processor core executes the MWAIT(C1) instruction.
Low Power Features 2.1.2.2 Stop-Grant State When the STPCLK# pin is asserted, each core of the quad-core processor enters the Stop-Grant state within 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current low power state. When the STPCLK# pin is deasserted, each core returns to its previous core low power state.
Low Power Features If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through the Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence.
Low Power Features 2.2 Enhanced Intel SpeedStep® Technology The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: • Multiple voltage and frequency operating points provide optimal performance at the lowest power.
Low Power Features operating point. Upon receiving a break event from the package low power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in the Stop-Grant and Deeper Sleep states. Note: Long-term reliability cannot be assured unless all the Extended Low Power States are enabled.
Low Power Features 2.4.1 Dual Intel Dynamic Acceleration The processor supports Dual Intel Dynamic Acceleration. For any two cores in the quad-core processor, the Dual Intel Dynamic Acceleration feature allows one core to operate at a higher frequency point while the other core is inactive and the operating system requests increased performance. Thus, quad-core processor could enter Dual Intel Dynamic Acceleration when two cores are idle and the other two are active.
Low Power Features 20 Datasheet
Electrical Specifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the processor will have a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Refer to the platform design guides for more details.
Electrical Specifications 3.3 Voltage Identification and Power Sequencing The processor uses seven voltage identification pins,VID[6:0], to support automatic selection of power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 3 specifies the voltage level corresponding to the state of VID[6:0]. A 1 in the table refers to a high-voltage level and a 0 refers to a low-voltage level.
Electrical Specifications Table 3. Datasheet Voltage Identification Definition (Sheet 1 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 0 0 0 0 0 0 1.5000 0 0 0 0 0 0 1 1.4875 0 0 0 0 0 1 0 1.4750 0 0 0 0 0 1 1 1.4625 0 0 0 0 1 0 0 1.4500 0 0 0 0 1 0 1 1.4375 0 0 0 0 1 1 0 1.4250 0 0 0 0 1 1 1 1.4125 0 0 0 1 0 0 0 1.4000 0 0 0 1 0 0 1 1.3875 0 0 0 1 0 1 0 1.3750 0 0 0 1 0 1 1 1.
Electrical Specifications Table 3. 24 Voltage Identification Definition (Sheet 2 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 1 0 0 1 0 1 1.0375 0 1 0 0 1 1 0 1.0250 0 1 0 0 1 1 1 1.0125 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.
Electrical Specifications Table 3. Datasheet Voltage Identification Definition (Sheet 3 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 1 0 1 0 1 0 0 0.4500 1 0 1 0 1 0 1 0.4375 1 0 1 0 1 1 0 0.
Electrical Specifications Table 3. 3.4 Voltage Identification Definition (Sheet 4 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 1 1 0 0 0 1 0.0875 1 1 1 0 0 1 0 0.0750 1 1 1 0 0 1 1 0.0625 1 1 1 0 1 0 0 0.0500 1 1 1 0 1 0 1 0.0375 1 1 1 0 1 1 0 0.0250 1 1 1 0 1 1 1 0.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.
Electrical Specifications 3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 4. Table 4. BSEL[2:0] Encoding for BCLK Frequency BSEL[2] 3.
Electrical Specifications Table 5. FSB Pin Groups Signal Group Signals1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, BNR#, BPM[3:0]#3, BPM_2[3:0]#3, BR0#, BR1#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3, DPWR# Signals AGTL+ Source Synchronous I/O Synchronous to assoc.
Electrical Specifications 3.8 CMOS Signals CMOS input signals are shown in Table 5. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than four BCLKs for the processor to recognize them. See Section 3.10 for DC specifications for the CMOS signal groups. 3.
Electrical Specifications 3.10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 5 for the pin signal definitions and signal pin assignments. The table below lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages.
Electrical Specifications Table 7. Voltage and Current Specifications for the Quad-Core Extreme Mobile Processors (Sheet 2 of 2) Symbol Parameter Min Typ Max Unit Notes 5, 7 dICC/DT VCC Power Supply Current Slew Rate at Processor Package Pin — — 600 A/µs ICCA ICC for VCCA Supply — — 130 mA ICCP ICC for VCCP Supply before VCC Stable ICC for VCCP Supply after VCC Stable — — 4.5 2.5 A A 8, 9 NOTES: 1.
Electrical Specifications Table 8. Voltage and Current Specifications for the Quad-Core Mobile Processors (Sheet 2 of 2) Symbol ICC Parameter Min Typ Max Unit Notes ICC for Processors — — — Processor Number Core Frequency/Voltage — — — Q9100 2.26 GHz & VCCHFM 1.60 GHz & VCCLFM — — 64 47 A 3, 4 Q9000 2.0 GHz & VCCHFM 1.60 GHz & VCCLFM — — 64 47 A 3, 4 IAH, ISGNT ICC Auto-Halt & Stop-Grant HFM LFM — — 32.4 30.0 A 3, 4 ISLP ICC Sleep HFM LFM — — 31.8 29.
Electrical Specifications Figure 4. Active VCC and ICC Loadline for Quad-Core Extreme Mobile Processor VCC-CORE [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 10mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Figure 5. Deeper Sleep VCC and ICC Loadline for Quad-Core Extreme Mobile Processor VCC-CORE [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 13mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Table 9. AGTL+ Signal Group DC Specifications (Sheet 2 of 2) RTT/A Termination Resistance Address 45 50 55 Ω 7, 12 RTT/D Termination Resistance Data 45 50 55 Ω 7, 13 RTT/Cntrl Termination Resistance Control 45 50 55 Ω 7, 14 RON/A Buffer On Resistance Address 8.25 8.33 12.25 Ω 5, 12 RON/D Buffer On Resistance Data 8.25 8.33 12.25 Ω 5, 13 RON/Cntrl Buffer On Resistance Control 8.25 8.33 12.25 Ω 5, 14 — — ± 100 µA 8 1.80 2.30 2.
Electrical Specifications Table 10. CMOS Signal Group DC Specifications Symbol VCCP Parameter I/O Voltage Min Typ Max Unit 1.00 1.05 1.10 V Notes1 VIL Input Low Voltage CMOS -0.10 0.00 0.3*VCCP V 2, 3 VIH Input High Voltage 0.7*VCCP VCCP VCCP+0.1 V 2 VOL Output Low Voltage -0.10 0 0.1*VCCP V 2 VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2 IOL Output Low Current 1.5 — 4.1 mA 4 IOH Output High Current 1.5 — 4.
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information 4.1 Package Mechanical Specifications The processor is available in a 478-pin Micro-FCPGA package. The package mechanical dimensions are shown in Figure 6 and Figure 7. The mechanical package pressure specifications are in a direction normal to the surface of the processor.
' ' 0.37 MAX 0.65 MAX *+,*-. /0123*2. 45.36788 7. ' P % % " " # ! $ ! ) #.
Datasheet # # EDGE KEEP OUT ZONE 4X 4 X 6.18 CORNER KEEP OUT ZONE 4x 4.3 1.5 MAX ALLOWABLE COMPONENT HEIGHT ø0.305±0.25 ø0.406 M C A B ø0.254 M C 13.97 " $ # % # 6.985 ! 6.985 " " D99017-2of2 13.97 1.625 1.625 Figure 7.
Package Mechanical Specifications and Pin Information 4.2 Processor Pinout and Pin List Figure 8 and Figure 9 shows the processor pinout as viewed from the top of the package. Table 12 provides the pin list, arranged numerically by pin name. Table 13 provides the pin list, arranged numerically by pin number. Table 14 is the signal description for processor. Table 15 lists new quad-core processor pins compared to the Intel Core 2 Duo processor. Figure 8.
Package Mechanical Specifications and Pin Information Figure 9.
Package Mechanical Specifications and Pin Information Table 12.
Package Mechanical Specifications and Pin Information Table 12. Pin Name Datasheet Pin Listing by Pin Name Pin # Signal Buffer Type Direction Table 12.
Package Mechanical Specifications and Pin Information Table 12. Pin Name Pin # Signal Buffer Type Direction Table 12.
Package Mechanical Specifications and Pin Information Table 12. Pin Name REQ[3]# REQ[4]# Datasheet Pin Listing by Pin Name Pin # J3 L1 Signal Buffer Type Direction Source Synch Input/ Output Source Synch Input/ Output Table 12.
Package Mechanical Specifications and Pin Information Table 12. Pin Name 46 Pin Listing by Pin Name Pin # Signal Buffer Type Direction Table 12.
Package Mechanical Specifications and Pin Information Table 12. Pin Name Datasheet Pin Listing by Pin Name Pin # Signal Buffer Type Direction Table 12.
Package Mechanical Specifications and Pin Information Table 12. Pin Name 48 Pin Listing by Pin Name Pin # Signal Buffer Type Direction Table 12.
Package Mechanical Specifications and Pin Information Table 13. Pin # Pin Name Signal Buffer Type Direction A2 VSS Power/Other A3 SMI# CMOS A4 VSS Power/Other A5 FERR# Open Drain Output A6 A20M# CMOS Input A7 VCC Power/Other Input Table 13.
Package Mechanical Specifications and Pin Information Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin # Pin Name Signal Buffer Type Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin # 52 Pin Listing by Pin Number Pin Name Signal Buffer Type Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin # Pin Name Signal Buffer Type E23 D[7]# Source Synch E24 VSS Power/Other E25 Datasheet Pin Listing by Pin Number D[6]# Direction Input/ Output Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin # Pin Name Signal Buffer Type J6 VCCP Power/Other J21 VCCP Power/Other J22 VSS Power/Other J23 D[11]# Source Synch J24 D[10]# Source Synch J25 VSS Power/Other J26 DSTBN[0]# Source Synch K1 VSS Power/Other K2 54 Pin Listing by Pin Number REQ[2]# Source Synch Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13. Pin # Pin Name Signal Buffer Type Direction Table 13.
Package Mechanical Specifications and Pin Information Table 13.
Package Mechanical Specifications and Pin Information Table 14. Signal Description (Sheet 1 of 9) Name A20M# Type Input Description If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal.
Package Mechanical Specifications and Pin Information Table 14. Signal Description (Sheet 2 of 9) Name Type BPM_2[1]# Output BPM_2[0;3:2] # Input/ Output Description BPM_2[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals of the second die. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM_2[3:0]# should connect the appropriate pins of all processor FSB agents.
Package Mechanical Specifications and Pin Information Table 14. Signal Description (Sheet 3 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period.
Package Mechanical Specifications and Pin Information Table 14. Signal Description (Sheet 4 of 9) Name Type Description DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle.
Package Mechanical Specifications and Pin Information Table 14. Signal Description (Sheet 5 of 9) Name FERR#/PBE# Type Output Description FERR# (Floating-point Error)/PBE# (Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error.
Package Mechanical Specifications and Pin Information Table 14. Signal Description (Sheet 6 of 9) Name IGNNE# Type Description Input IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a non-control floating-point instruction if a previous floating-point instruction caused an error.
Package Mechanical Specifications and Pin Information Table 14. Signal Description (Sheet 7 of 9) Name PROCHOT# Type Input/ Output Description As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled.
Package Mechanical Specifications and Pin Information Table 14. Signal Description (Sheet 8 of 9) Name RSVD SLP# SMI# Type Description Reserved/ No Connect These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state.
Package Mechanical Specifications and Pin Information Table 14. Signal Description (Sheet 9 of 9) Name Type Description TEST1, TEST2, TEST3, TEST4, Input Refer to the appropriate platform design guide for further TEST1, TEST2, TEST3, TEST4, TEST5, TEST6 and TEST7 termination requirements and implementation details. Output The processor protects itself from catastrophic overheating by use of an internal thermal sensor.
Package Mechanical Specifications and Pin Information Table 15. New Pins for the Quad-Core Mobile Processor Pin Name Pin# Description BPM_2[0]# N5 BPM_2[1]# M4 BPM_2[2]# B2 BPM_2[3]# AE8 BPM_2[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals of the second die. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits. Caution: Operating the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. Maintaining the proper thermal environment is key to reliable, long-term system operation.
Thermal Specifications and Design Considerations 5. 6. 7. 8. 5.1 Processor TDP requirements in Intel Dynamic Acceleration mode are lesser than TDP in HFM. At Tj of 100oC At Tj of 50oC At Tj of 35oC Monitoring Die Temperature The processor incorporates three methods of monitoring die temperature: • Thermal Diode • Intel® Thermal Monitor • Digital Thermal Sensor Note: The Intel Thermal Monitor (detailed in Section 5.1.
Thermal Specifications and Design Considerations Table 17. Table 18.
Thermal Specifications and Design Considerations temperature. The Intel Thermal Monitor uses two modes to activate the TCC: automatic mode and on-demand mode. If both modes are activated, automatic mode takes precedence. There are two automatic modes called Intel Thermal Monitor 1 (TM1) and Intel Thermal Monitor 2 (TM2). These modes are selected by writing values to the MSRs of the processor.
Thermal Specifications and Design Considerations Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Thermal Specifications and Design Considerations Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details. 5.
