Intel® Celeron® Dual-Core Processor E1000Δ Series Datasheet January 2008 Document Number: 318924-001
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Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Terminology ............................................................................ 10 1.2 References .......................................................................................................
5.3 5.4 5.2.2 Thermal Monitor 2 ..................................................................................77 5.2.3 On-Demand Mode ...................................................................................78 5.2.4 PROCHOT# Signal ..................................................................................79 5.2.5 THERMTRIP# Signal ................................................................................79 Thermal Diode............................................................
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Datasheet VCC Static and Transient Tolerance for Processors......................................................... 21 VCC Overshoot Example Waveform ............................................................................. 22 Differential Clock Waveform ...................................................................................... 30 Differential Clock Crosspoint Specification ...........................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 6 References ..............................................................................................................11 Voltage Identification Definition ..................................................................................15 Market Segment Selection Truth Table for MSID[1:0] ...................................................16 Absolute Maximum and Minimum Ratings .......................
Intel® Celeron® Dual-Core Processor E1000Δ Series • • • • • Available at 1.
Revision History Revision Number -001 Description • Initial release Date January 2008 §§ 8 Datasheet
Introduction 1 Introduction The Intel® Celeron® Dual-Core processor E1000 series combines the performance of the current generation of desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. These dual-core processors are based on 65 nm process technology. They are 64-bit processors that maintain compatibility with IA-32 software.
Introduction 1.1.1 Processor Terminology Commonly used terms are explained here for clarification: • Intel® Celeron® Dual-Core processor E1000 series — Dual core processor in the FC-LGA6 package with a 512 KB L2 cache. • Processor — For this document, the term processor is the generic form of the Intel® Celeron® Dual-Core processor E1000 series. The processor is a single package that contains one or more execution units. • Keep-out zone — The area on or near the processor that system design can not use.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1. References Document Location Intel® Celeron® Dual-Core Processor E1000 Series Specificaiton Update www.intel.com/design/ processor/specupdt/ 318925.htm Intel® Core™2 Duo Processor, Intel® Pentium® Dual Core, and Intel® Celeron® Dual-Core Processor Thermal and Mechanical Design Guidelines http://www.intel.com/ design/processor/ designex/317804.
Introduction 12 Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.
Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 1 1 1 1 0 1 0.8500 0 1 1 1 1 0 1.2375 1 1 1 1 0 0 0.8625 0 1 1 1 0 1 1.2500 1 1 1 0 1 1 0.8750 0 1 1 1 0 0 1.2625 1 1 1 0 1 0 0.8875 0 1 1 0 1 1 1.2750 1 1 1 0 0 1 0.9000 0 1 1 0 1 0 1.2875 1 1 1 0 0 0 0.9125 0 1 1 0 0 1 1.3000 1 1 0 1 1 1 0.9250 0 1 1 0 0 0 1.3125 1 1 0 1 1 0 0.9375 0 1 0 1 1 1 1.
Electrical Specifications 2.4 Market Segment Identification (MSID) The MSID[1:0] signals may be used as outputs to determine the Market Segment of the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can be used to prevent 130 W TDP processors from booting on boards optimized for 65 W TDP. Table 3.
Electrical Specifications The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below.
Electrical Specifications Table 4. Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes1, 2 VCC Core voltage with respect to VSS –0.3 1.55 V - VTT FSB termination voltage with respect to VSS –0.3 1.55 V - TC Processor case temperature See Chapter 5 See Chapter 5 °C - TSTORAGE Processor storage temperature –40 85 °C 3, 4, 5 NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.
Electrical Specifications 2.6.2 DC Voltage and Current Specification Table 5. Voltage and Current Specifications Symbol VID Range Parameter VID Processor Number VCC VCC for 775_VR_CONFIG_06 E1200 1.6 GHz VCC_BOOT Default VCC voltage for initial power up VCCPLL PLL VCC Processor Number ICC VTT VTT_OUT_LEFT and VTT_OUT_RIGHT ICC ITT VCC for 775_VR_CONFIG_06 E1200 Typ Max Unit 0.8500 — 1.5 V 3 Refer to Table 6 and Figure 1 V 4, 5, 6 — 1.10 — V - 5% 1.50 + 5% — — 1.
Electrical Specifications Table 6. VCC Static and Transient Tolerance for Processors Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.30 mΩ Typical Voltage 1.425 mΩ Minimum Voltage 1.55 mΩ 0 0.000 -0.019 -0.038 5 -0.007 -0.026 -0.046 10 -0.013 -0.033 -0.054 15 -0.020 -0.040 -0.061 20 -0.026 -0.048 -0.069 25 -0.033 -0.055 -0.077 30 -0.039 -0.062 -0.085 35 -0.046 -0.069 -0.092 40 -0.052 -0.076 -0.100 45 -0.059 -0.083 -0.108 50 -0.
Electrical Specifications Figure 1. VCC Static and Transient Tolerance for Processors ICC (A) 0 10 VID – 0.000 VID – 0.013 20 40 30 VID – 0.025 50 60 70 VCC Maximum VID – 0.038 VID – 0.050 VID – 0.063 VCC (V) VID – 0.075 VID – 0.088 VCC Typical VID – 0.100 VID – 0.113 VCC Minimum VID – 0.125 VID – 0.138 VID – 0.150 VID – 0.163 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3. 2.
Electrical Specifications Figure 2. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.6.4 Die Voltage Validation Overshoot events on processor must meet the specifications in Table 7 when measured across the VCC_SENSE and VSS_SENSE lands.
Electrical Specifications 2.7.1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.
Electrical Specifications 3. 4. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details. PROCHOT# signal type is open drain output and CMOS input. . Table 9.
Electrical Specifications 2.7.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. Table 11. GTL+ Signal Group DC Specifications Symbol VIL Parameter Input Low Voltage Notes1 Min Max Unit -0.10 GTLREF – 0.10 V 2, 3 GTLREF + 0.10 VTT + 0.10 V 4, 5, 3 Output High Voltage VTT – 0.
Electrical Specifications . Table 13. CMOS Signal Group DC Specifications Symbol VIL Parameter Input Low Voltage Notes1 Min Max Unit -0.10 VTT * 0.30 V 2, 3 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V 4, 5, 3 VOL Output Low Voltage -0.10 VTT * 0.10 V 3 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 6, 5, 3 IOL Output Low Current 1.70 4.70 mA 3, 7 IOH Output High Current 1.70 4.
Electrical Specifications Table 14. GTL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes1 GTLREF_PU GTLREF pull up resistor on 975X and 96x Express Chipset family boards 124 * 0.99 124 124 * 1.01 Ω 2 GTLREF_PD GTLREF pull down resistor on 975X and 96x Express Chipset family boards 210 * 0.99 210 210 * 1.01 Ω 2 GTLREF_PU GTLREF pull up resistor on Intel Series 3 Express Chipset family boards 100 * 0.99 100 100 * 1.
Electrical Specifications 2.8 Clock Specifications 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. Refer to Table 15 for the processor supported ratios.
Electrical Specifications Table 16. 2.8.3 BSEL[2:0] Frequency Table for BCLK[1:0] BSEL2 BSEL1 BSEL0 FSB Frequency L L L RESERVED L L H RESERVED L H H RESERVED L H L 200 MHz H H L RESERVED H H H RESERVED H L H RESERVED H L L RESERVED Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 5 for DC specifications. 2.8.
Electrical Specifications Figure 3. Differential Clock Waveform CLK 0 VCROSS Median + 75 mV VCROSS median VCROSS VCROSS Max 550 mV VCROSS VCROSS Min 300 mV Median - 75 mV CLK 1 High Time median Low Time Period Figure 4. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 300 + 0.5 (VHavg - 700) 350 300 250 300 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 5.
Electrical Specifications 2.8.5 BCLK[1:0] Specifications (CK410 based Platforms) Table 18. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input Low Voltage -0.150 0.00 0 N/A V 3 - VH Input High Voltage 0.660 0.70 0 0.850 V 3 - VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 3, 4 2, 3 VCROSS(rel) Relative Crossing Point 0.250 + 0.5(VHavg – 0.700) N/A 0.550 + 0.5(VHavg – 0.
Electrical Specifications 2.9 PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors (may also include chipset components in the future) and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die.
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 8.
Package Mechanical Specifications Figure 9.
Package Mechanical Specifications Figure 10.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 8 and Figure 9 for keep-out zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 12.
Package Mechanical Specifications 40 Datasheet
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 13 and Figure 14. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 13.
Land Listing and Signal Descriptions Figure 14.
Land Listing and Signal Descriptions Table 23. Land Name 44 Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 46 Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 48 Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 50 Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 52 Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name VSS Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 24. Land # 54 Numerical Land Assignment Land Name Signal Buffer Type A2 VSS Power/Other A3 RS2# Common Clock A4 D02# A5 D04# Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name C20 DBI3# C21 D58# C22 VSS C23 C24 Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. 56 Numerical Land Assignment Land # Land Name F11 D23# F12 D24# Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions Table 24. Land # 58 Numerical Land Assignment Land Name Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type U28 VCC U29 U30 Table 24.
Land Listing and Signal Descriptions Table 24. 60 Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type AF12 VCC Table 24.
Land Listing and Signal Descriptions Table 24. Land # 62 Numerical Land Assignment Land Name Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type AL18 VCC AL19 AL20 Table 24.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 25. Signal Description (Sheet 1 of 9) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 2 of 9) Name Type Description BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents. BPM[5:0]# Input/ Output BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 3 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 4 of 9) Name DEFER# DRDY# Type Description Input DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 5 of 9) Name HIT# HITM# IERR# Type Input/ Output Input/ Output Output Description HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 6 of 9) Name Type Description LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. LOCK# Input/ Output MSID[1:0] Output These signals indicate the Market Segment for the processor.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 7 of 9) Name Type Description RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents. SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 8 of 9) Name THERMTRIP# Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 9 of 9) Name Type Description VRDSEL Input This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to VSS. VSS Input VSS are the ground pins for the processor and should be connected to the system ground plane. VSSA Input VSSA is the isolated ground for internal PLLs.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as described in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption.
Thermal Specifications and Design Considerations Table 27. Figure 15. Datasheet Thermal Profile Power (W) Maximum Tc (°C) Power Maximum Tc (°C) Power Maximum Tc (°C) 0 45.3 24 55.6 48 65.9 2 46.2 26 56.5 50 66.8 4 47.0 28 57.3 52 67.7 6 47.9 30 58.2 54 68.5 8 48.7 32 59.1 56 69.4 10 49.6 34 59.9 58 70.2 12 50.5 36 60.8 60 71.1 14 51.3 38 61.6 62 72.0 16 52.2 40 62.5 64 72.8 18 53.0 42 63.4 65 73.3 20 53.9 44 64.2 22 54.8 46 65.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 26. This temperature specification is meant to help ensure proper operation of the processor. Figure 16 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). Figure 16.
Thermal Specifications and Design Considerations under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.
Thermal Specifications and Design Considerations Figure 17. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 Temperature fMAX fTM2 Frequency VID VIDTM2 VID PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on demand mode.
Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Thermal Specifications and Design Considerations 5.3 Thermal Diode The processor incorporates an on-die PNP transistor where the base emitter junction is used as a thermal "diode", with its collector shorted to ground. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control. Table 28,Table 29, and Table 30 provide the "diode" parameter and interface specifications.
Thermal Specifications and Design Considerations Table 29. Thermal “Diode” Parameters using Transistor Model Symbol Parameter Min Typ Max Unit Notes µA 1, 2 - 3, 4, 5 Ω 3, 6 IFW Forward Bias Current 5 — 200 IE Emitter Current 5 — 200 nQ Transistor Ideality 0.997 1.001 1.005 0.391 — 0.760 2.79 4.52 6.24 Beta RT Series Resistance 3, 4 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 28. 3.
Thermal Specifications and Design Considerations 5.4 Platform Environment Control Interface (PECI) 5.4.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. Figure 18 shows an example of the PECI topology in a system. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices.
Thermal Specifications and Design Considerations . Figure 19. Conceptual Fan Control on PECI-Based Platforms TCONTROL Setting TCC Activation Temperature PECI = 0 Max Fan Speed (RPM) PECI = -10 Min PECI = -20 Temperature Note: Not intended to depict actual implementation . Figure 20.
Thermal Specifications and Design Considerations 5.4.2 PECI Specifications 5.4.2.1 PECI Device Address The PECI device address for the socket is 30h. For more information on PECI domains, refer to the Platform Environment Control Interface Specification. 5.4.2.2 PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported PECI command function and codes. 5.4.2.
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 32. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 21 for a visual representation of the processor low power states. Figure 21.
Features 6.2.2.1 HALT Powerdown State HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted, however, the other processor continues normal operation. The processor will transition to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.
Features 6.2.3.1 Stop-Grant State When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state.
Features 6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State The processor will remain in the lower bus ratio and VID operating point of the Extended HALT state or Extended Stop Grant state. While in the Extended HALT Snoop State or Extended Stop Grant Snoop State, snoops are handled the same way as in the HALT Snoop State or Stop Grant Snoop State. After the snoop is serviced, the processor will return to the Extended HALT state or Extended Stop Grant state. 6.
Features 90 Datasheet
Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 22 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 24. Space Requirements for the Boxed Processor (Top View) NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 25.
Boxed Processor Specifications 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications Figure 26. Boxed Processor Fan Heatsink Power Cable Connector Description Pin 1 2 3 4 Signal GND +12 V SENSE CONTROL Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on mainboard. 1 2 3 4 B Table 33. d P P C bl Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes 11.4 12 12.
Boxed Processor Specifications Figure 27. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33] B C Boxed Proc PwrHeaderPlacement 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 28. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) Figure 29.
Boxed Processor Specifications 7.3.2 Fan Speed Control Operation If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Boxed Processor Specifications Table 34. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed X ≤ 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. 1 Y = 35 When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Boxed Processor Specifications 100 Datasheet
Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
Debug Tools Specifications 102 Datasheet
