Datasheet

Intel
®
Celeron
®
M Processor Datasheet 7
Introduction
1 Introduction
The Intel
®
Celeron
®
M processor and the ultra low voltage (ULV) Intel
®
Celeron
®
M processor
are high-performance, low-power mobile processors with several microarchitectural enhancements
over existing mobile Intel Celeron processors.
The Intel Celeron M processor is available at the following core frequencies in the Micro-FCBGA
and Micro-FCPGA packaging technologies:
• 1.20 GHz (1.356 V)
• 1.30 GHz (1.356 V)
• 1.40 GHz (1.356 V)
• 1.50 GHz (1.356 V)
The ultra low voltage Intel Celeron M processor is available at the following frequency in the
Micro-FCBGA packaging technology:
• 800 MHz (1.004 V)
• 900 MHz (1.004 V)
The Micro-FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF)
socket, which is referred to as the mPGA479M socket.
The following list provides some of the key features of this processor:
• Supports Intel architecture with dynamic execution
• Manufactured on Intel’s advanced 0.13 micron process technology with copper interconnect.
• High-performance, low-power core featuring architectural innovations like micro-ops fusion
and advanced stack management that reduce the number of micro-ops handled by the
processor.
• On-die, primary 32-kB instruction cache and 32-kB, write-back, data cache
• On-die, 512-kB second level cache with Advanced Transfer Cache architecture
• Advanced branch prediction and data prefetch logic
• Streaming SIMD extensions 2 (SSE2) that enables breakthrough levels of performance in
multimedia applications including 3D graphics, video decoding/encoding, and speech
recognition.
• 400-MHz, source-synchronous front side bus (FSB)
• Advanced power management features
• Maintained support for MMX
TM
technology
• Compatible with IA-32 software.
The processor also features a very advanced branch prediction architecture that significantly
reduces the number of mispredicted branches. The processor’s Data Prefetch Logic speculatively
fetches data to the L2 cache before an L1 cache request occurs, resulting in reduced bus cycle
penalties and improved performance.