User Manual

92 Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
7.2 Signal Summaries
Table 43 through Table 46 list attributes of the processor output, input, and I/O signals.
VID[3:0] O
The VID[3:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to V
SS on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on processors. See Table 2 for definitions of these
pins. The power supply must supply the voltage that is requested by these pins, or
disable itself.
V
CORE
DET
O
The V
CORE
DET
pin indicate the type of processor core present. This pin will float for
2.0 V V
CC
CORE
based processor and will be shorted to VSS for the Pentium III
processor.
V
CC
1.5
I
The V
CC
1.5
V input pin provides the termination voltage for CMOS signals
interfacing to the processor. The Pentium III processor reroutes the 1.5 V input to
the V
CC
CMOS
output via the package. The supply for VCC
1.5
V must be the same one
used to supply V
TT
.
VCC
2.5
I
The V
CC
2.5
V input pin provides the termination voltage for CMOS signals
interfacing to processors which require 2.5 V termination on the CMOS signals. This
signal is not used by the Pentium III processor.
V
CC
CMOS
O
The VccCMOS pin provides the CMOS voltage for use by the platform and is used
for terminating CMOS signals that interface to the processor.
V
REF
I
The V
REF
input pins supply the AGTL+ reference voltage, which is typically 2/3 of
V
TT.V
REF
is used by the AGTL+ receivers to determine if a signal is a logical 0 or a
logical 1.
Table 42. Signal Description (Sheet 8 of 8)
Name Type Description
Table 43. Output Signals
Name Active Level Clock Signal Group
CPUPRES# Low Asynch Power/Other
EDGCTRL N/A Asynch Power/Other
FERR# Low Asynch CMOS Output
IERR# Low Asynch CMOS Output
PRDY# Low BCLK AGTL+ Output
THERMTRIP# Low Asynch CMOS Output
V
CORE
DET
N/A Asynch Power/Other
VID[3:0] N/A Asynch Power/Other
Table 44. Input Signals (Sheet 1 of 2)
Name Active Level Clock Signal Group Qualified
A20M# Low Asynch CMOS Input Always
1
BCLK High — System Bus Clock Always
BPRI# Low BCLK AGTL+ Input Always
BR1# Low BCLK AGTL+ Input Always