User Manual

Datasheet 5
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figures
1 Second Level (L2) Cache Implementation ...........................................................8
2 AGTL+/AGTL Bus Topology in a Uniprocessor Configuration ............................14
3 AGTL+/AGTL Bus Topology in a Dual-Processor Configuration ........................14
4 Stop Clock State Machine...................................................................................15
5 Processor Vcc
CMOS
Package Routing ................................................................18
6 Differential Clocking Example .............................................................................20
7 BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design .........25
8 Slew Rate (23A Load Step).................................................................................33
9 Generic Clock Waveform ....................................................................................41
10 BCLK, PICCLK, and TCK Generic Clock Waveform...........................................42
11 System Bus Valid Delay Timings ........................................................................42
12 System Bus Setup and Hold Timings..................................................................43
13 System Bus Reset and Configuration Timings....................................................43
14 Platform Power-On Sequence Timings ...............................................................44
15 Power-On Reset and Configuration Timings.......................................................45
16 BCLK, PICCLK Generic Clock Waveform at the Processor Pins........................47
17 Low to High AGTL+ Receiver Ringback Tolerance.............................................48
18 Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform.......................53
19 Maximum Acceptable AGTL Overshoot/Undershoot Waveform.........................53
20 Non-AGTL+ (Non-AGTL) Overshoot/Undershoot, Settling Limit, and
Ringback 1 ..........................................................................................................54
21 Processor Functional Die Layout for FC-PGA.....................................................58
22 FC-PGA and FC-PGA2 Package Types .............................................................60
23 Package Dimensions...........................................................................................61
24 Package Dimensions for FC-PGA2.....................................................................63
25 FC-PGA2 Flatness Specification.........................................................................64
26 Top Side Processor Markings for FC-PGA (up to CPUID 0x686H) ....................65
27 Top Side Processor Markings for FC-PGA (for CPUID 0x68AH)).......................65
28 Top Side Processor Markings for FC-PGA2 .......................................................66
29 Volumetric Keep-Out for FC-PGA and FC-PGA2................................................66
30 Component Keep-Out .........................................................................................67
31 Intel
®
Pentium
®
III Processor Pinout...................................................................68
32 Conceptual Boxed Intel
®
Pentium
®
III Processor for the PGA370 Socket..........80
33 Dimensions of Mechanical Step Feature in Heatsink Base.................................81
34 Dimensions of Notches in Heatsink Base ...........................................................82
35 Thermal Airspace Requirement for all Boxed Intel
®
Pentium
®
III Processor Fan
Heatsinks in the PGA370 Socket ........................................................................83
36 Boxed Processor Fan Heatsink Power Cable Connector Description.................84
37 Motherboard Power Header Placement Relative to the Boxed
Intel
®
Pentium
®
III Processor ..............................................................................84