User Manual

Datasheet 47
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the V
IH (rising) or VIL (falling) voltage limits.
This specification is an absolute value.
3.2 AGTL+ / AGTL Signal Quality Specifications and
Measurement Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in the appropriate platform design guide. Refer to the Intel
®
Pentium
®
II Processor
Developer's Manual (Order Number 243502) for the AGTL+/AGTL buffer specification.
Table 23 provides the AGTL+ signal quality specifications for the processor for use in simulating
signal quality at the processor pins.
The Pentium
III processor for the PGA370 socket maximum allowable overshoot and undershoot
specifications for a given duration of time are detailed in Table 25 through Table 27. Figure 17
shows the AGTL+/AGTL ringback tolerance and Figure 18 shows the overshoot/undershoot
waveform.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. Specifications are for the edge rate of 0.3 - 0.8V/ns. See Figure 17 for the generic waveform.
3. All values specified by design characterization.
4. Please see Table 25 for maximum allowable overshoot.
5. Ringback between V
REF
+ 100 mV and V
REF
+ 200 mV or V
REF
- 200 mV and V
REF
- 100 mVs requires the
flight time measurements to be adjusted as described in the Intel AGTL+ Specifications (Intel
®
Pentium
®
II
Developers Manual). Ringback below V
REF
+ 100 mV or above V
REF
- 100 mV is not supported.
Figure 16. BCLK, PICCLK Generic Clock Waveform at the Processor Pins
V2
V1
V3
V3
V4
V5
Table 23. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor
Pins
1, 2, 3
T# Parameter Min Unit Figure Notes
α: Overshoot 100 mV 17 4, 8
τ: Minimum Time at High 0.50 ns 17
ρ: Amplitude of Ringback ±200 mV 17 5, 6, 7, 8
φ: Final Settling Voltage 200 mV 17 8
δ: Duration of Squarewave Ringback N/A ns 17