User Manual

Datasheet 37
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.12 System Bus AC Specifications
The processor system bus timings specified in this section are defined at the socket pins on the
bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins
during manufacturing. Timings at the processor pins are specified by design characterization. See
Section 7.0 for the processor signal definitions.
Table 14 through Table 20 list the AC specifications associated with the processor system bus.
These specifications are placed into the following categories: Table 14 and Table 15 contain the
system bus clock specifications, Table 16 contains the AGTL+/AGTL specifications, Table 17
contains the CMOS signal group specifications, Table 18 contains timings for the reset conditions,
Table 19 and covers APIC bus timing, and Table 20 covers power on timing.
All processor system bus AC specifications for the AGTL+/AGTL signal group are relative to the
rising edge of the BCLK input. All AGTL+/AGTL timings are referenced to V
REF
for both ‘0’ and
‘1’ logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Pentium
III processor in the FC-PGA package in Viewlogic* XTK/XNS* model format
(formerly known as QUAD format) and IBIS * 3.1 format as the Pentium III Processor for the
PGA370 Socket I/O Buffer Models (Electronic Format).
AGTL and AGTL+ layout guidelines are also available in the appropriate platform design guide.
Care should be taken to read all notes associated with a particular timing parameter.
2.12.1 I/O Buffer Model
An electronic copy of the I/O Buffer Model for the AGTL+ and CMOS signals is available at
Intel’s Developer’s Website (http://developer.intel.com). The model is for use in single processor
designs and assumes the presence of motherboard R
TT
values as described in Table12onpage36.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pin.
All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor pins.
Table 14. System Bus AC Specifications (SET Clock)
1, 2
T# Parameter Min Nom Max Unit Figure Notes
System Bus Frequency
100.00
133.33
MHz 4
T1: BCLK Period
10.0
7.5
ns 9
4, 5, 10
4, 5, 11
T2: BCLK Period Stability
±250
±250
ps
6, 7, 10
6, 7, 11
T3: BCLK High Time
2.5
1.4
ns 9
9, 10
9, 11
T4: BCLK Low Time
2.4
1.4
ns 9
9, 10
9, 11
T5: BCLK Rise Time 0.4 1.6 ns 9 3, 8
T6: BCLK Fall Time 0.4 1.6 ns 9 3, 8