User Manual

36 Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.11 AGTL / AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to V
TT. These termination resistors are placed electrically between the ends of the signal
traces and the V
TT voltage supply and generally are chosen to approximate the system platform
impedance. The valid high and low levels are determined by the input buffers using a reference
voltage called V
REF
. Refer to the appropriate platform design guide for more information
Table 12 below lists the nominal specification for the AGTL+ termination voltage (V
TT). The
AGTL+ reference voltage (V
REF
) is generated on the system motherboard and should be set to 2/3
V
TT for the processor and other AGTL+ logic. It is important that the baseboard impedance be
specified and held to a ±15% tolerance, and that the intrinsic trace capacitance for the AGTL+
signal group traces is known and well-controlled. For more details on the AGTL+ buffer
specification, see the Intel
®
Pentium
®
II Processor Developer's Manual and AP-585,
Intel
®
Pentium
®
II Processor AGTL+ Guidelines.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. Pentium III processors for the PGA370 socket contain AGTL+ termination resistors on the processor die,
except for the RESET# input.
3. V
TT and Vcc
1.5
must be held to 1.5 V ±9%. It is required that VTT and Vcc
1.5
be held to 1.5 V ±3% while the
processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom
side of the baseboard.
4. The value of the on-die R
TT
is determined by the resistor value measured by the RTTCTRL signal pin. See
Section 7.0 for more details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific
chipset/processor combination.
5. V
REF
is generated on the motherboard and should be 2/3 VTT ±2% nominally. Insure that there is adequate
V
REF
decoupling on the motherboard.
NOTES:
1. Specifications in this table do not apply to Pentium III processors at all frequencies. Please refer to the
Intel
®
Pentium
®
III Processor Specification Update for a complete listing on the processors that support the
AGTL specification.
2. Pentium III processors for the PGA370 socket contain AGTL termination resistors on the processor die,
except for the RESET# input.
3. V
TT must be held to 1.25 V ±9%. It is required that VTT be held to 1.25 V ±3% while the processor system bus
is idle (static condition). This is measured at the PGA370 socket pins on the bottom side of the baseboard.
4. The value of the on-die R
TT
is determined by the resistor value measured by the RTTCTRL signal pin. The
on-die R
TT
has a resistance tolerance of ±15%. See Section 7.0 for more details on the RTTCTRL signal.
Refer to the recommendation guidelines for the specific chipset/processor combination.
5. V
REF
is generated on the motherboard and should be 2/3 VTT ±2% nominally. Insure that there is adequate
V
REF
decoupling on the motherboard.
6. For the Coppermine-T differential clock platform, the on-die RTT min should be 50 Ω.
7. Coppermine-T UP platforms require a 56Ω resistor and Coppermine-T DP platforms require a 68Ω resistor.
Tolerance for the on-die R
TT
is ±10% for 56Ω and 68Ω resistors and ±15% for 100 Ω resistors
Table 12. Processor AGTL+ Bus Specifications
1, 2
Symbol Parameter Min Typ Max Units Notes
V
TT Bus Termination Voltage 1.50 V 3
On-die R
TT
Termination Resistor 40 130 Ω 4
V
REF
Bus Reference Voltage 0.950 2/3 VTT 1.05 V 5
Table 13. Processor AGTL Bus Specifications
1, 2
Symbol Parameter Min Typ Max Units Notes
V
TT Bus Termination Voltage 1.14 1.25 1.308 V 3
On-die R
TT
Termination Resistor 50
6
56, 68 115 Ω 4, 7
V
REF
Bus Reference Voltage 2/3 VTT -2% 2/3VTT 2/3 VTT +2% V 5