Datasheet

Intel Desktop Board D865PERL Technical Product Specification
28
1.7 Intel
®
865PE Chipset
The Intel 865PE chipset consists of the following devices:
• Intel 82865PE Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus
• Intel 82801EB I/O Controller Hub (ICH5) with AHA bus or Intel 82801ER I/O Controller
HUB (ICH5-R)
• Intel 82802AB (4 Mbit) Firmware Hub (FWH)
The MCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
Accelerated Hub Architecture interface. The ICH5 is a centralized controller for the Desktop
Board D865PERL’s I/O paths. The FWH provides the nonvolatile storage of the BIOS. The
component combination provides the chipset interfaces as shown in Figure 8.
865PE Chipset
82801EB (ICH5) or
82801ER (ICH5-R)
I/O Controller Hub
82865PE
Memory Controller
Hub (MCH)
82802AB
4 Mbit Firmware
Hub (FWH)
AHA
Bus
System Bus
Parallel ATA
IDE Interface
USB
AGP
Interface
OM16103
CSMA/CD
Interface
AC Link
PCI
Bus
SMBus
Dual-Channel
DDR SDRAM
Bus
LPC Bus
Serial
ATA
IDE
Interface
CSA
Interface
Figure 8. Intel 865PE Chipset Block Diagram
For information about Refer to
The Intel 865PE chipset http://developer.intel.com
Resources used by the chipset Chapter 2
1.7.1 AGP
The AGP connector supports the following:
• 4x, 8x AGP 3.0 add-in cards with 0.8 V I/O
• 1x, 4x AGP 2.0 add-in cards with 1.5 V I/O
AGP is a high-performance interface for graphics-intensive applications, such as 3D applications.
While based on the PCI Local Bus Specification, Rev. 2.2, AGP is independent of the PCI bus and