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Table 2. Release Information
Item Description
Version 17.1
Release Date Novermber 2017
Ordering Code IP-BCH (IPR-BCH)
Intel verifies that the current version of the Quartus Prime software compiles the
previous version of each IP core. Intel does not verify that the Quartus Prime software
compiles IP core versions older than the previous version. The Intel FPGA IP Release
Notes lists any exceptions.
Related Information
• Intel FPGA IP Release Notes
• Errata for BCH IP core in the Knowledge Base
1.5. DSP IP Core Verification
Before releasing a version of an IP core, Intel runs comprehensive regression tests to
verify its quality and correctness. Intel generates custom variations of the IP core to
exercise the various parameter options and thoroughly simulates the resulting
simulation models with the results verified against master simulation models.
1.6. BCH IP Core Performance and Resource Utilization
Typical expected performance for a BCH IP Core using the Quartus Prime software
with the Arria V (5AGXFB3H4F35C5), Cyclone V (5CGXFC7C7F23C8), and Stratix V
(5SGXEA7H3F35C3) devices. Where m is the number of bits per symbol; n is the
codeword length; d is the parallel data input width; t is the error correction capability.
Table 3. Decoder Performance and Resource Utilization
Device Parameters Memory ALM Registers f
MAX
(MHz)
m n d t M10K M20K Primary Secondar
y
Arria V 8 255 10 42 7 -- 18,376 40,557 3,441 196
Cyclone V 8 255 10 42 7 -- 18,264 40,709 3,266 150
Stratix V 8 255 10 42 -- 7 19,027 44,134 4,315 308
Arria V 8 255 12 42 9 -- 22,293 49,602 4,053 186
Cyclone V 8 255 12 42 9 -- 22,243 49,243 4,511 149
Stratix V 8 255 12 42 -- 8 23,187 53,800 5,207 310
Arria V 8 255 2 42 4 -- 5,539 13,238 788 207
Cyclone V 8 255 2 42 4 -- 5,527 13,174 857 174
Stratix V 8 255 2 42 -- 4 6,088 14,399 850 369
Arria V 8 255 5 42 5 -- 10,231 23,321 1,554 206
Cyclone V 8 255 5 42 5 -- 10,234 23,391 1,551 164
continued...
1. About the BCH IP Core
683320 | 2017.11.06
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BCH IP Core: User Guide
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