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1.3. DSP IP Core Device Family Support
Intel offers the following device support levels for Intel FPGA IP cores:
• Advance support—the IP core is available for simulation and compilation for this
device family. FPGA programming file (.pof) support is not available for Quartus
Prime Pro Stratix 10 Edition Beta software and as such IP timing closure cannot be
guaranteed. Timing models include initial engineering estimates of delays based
on early post-layout information. The timing models are subject to change as
silicon testing improves the correlation between the actual silicon and the timing
models. You can use this IP core for system architecture and resource utilization
studies, simulation, pinout, system latency assessments, basic timing assessments
(pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O
standards tradeoffs).
• Preliminary support—Intel verifies the IP core with preliminary timing models for
this device family. The IP core meets all functional requirements, but might still be
undergoing timing analysis for the device family. You can use it in production
designs with caution.
• Final support—Intel verifies the IP core with final timing models for this device
family. The IP core meets all functional and timing requirements for the device
family. You can use it in production designs.
Table 1. DSP IP Core Device Family Support
Device Family Support
Arria
®
II GX Final
Arria II GZ Final
Arria V Final
Intel Arria 10 Final
Cyclone
®
IV Final
Cyclone V Final
Intel Cyclone 10 Final
Intel MAX
®
10 FPGA Final
Stratix
®
IV GT Final
Stratix IV GX/E Final
Stratix V Final
Intel Stratix 10 Advance
Other device families No support
1.4. BCH IP Core Release Information
Use the release information when licensing the IP core.
1. About the BCH IP Core
683320 | 2017.11.06
BCH IP Core: User Guide
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