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1. About the BCH IP Core
Related Information
• BCH IP Core Document Archive on page 24
Provides a list of user guides for previous versions of the BCH IP Core IP core.
• Introduction to Intel FPGA IP Cores
Provides general information about all Intel FPGA IP cores, including
parameterizing, generating, upgrading, and simulating IP cores.
• Creating Version-Independent IP and Qsys Simulation Scripts
Create simulation scripts that do not require manual updates for software or IP
version upgrades.
• Project Management Best Practices
Guidelines for efficient management and portability of your project and IP files.
1.1. Intel
®
DSP IP Core Features
• Avalon
®
Streaming (Avalon-ST) interfaces
• DSP Builder for Intel
®
FPGAs ready
• Testbenches to verify the IP core
• IP functional simulation models for use in Intel-supported VHDL and Verilog HDL
simulators
1.2. BCH IP Core Features
High-performance fully parameterizable encoder or decoder for error detection and
correction:
• Number of symbols per codeword
• Number of check symbols per codeword
• Number of parallel input bits
683320 | 2017.11.06
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