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Table 9. Avalon-ST Input and Output Interface Signals
Name Avalon-ST Type Direction Description
ready ready
Output Data transfer ready signal to indicate that the sink is ready
to accept data. The sink interface drives the ready signal to
control the flow of data across the interface. The sink
interface captures the data interface signals on the current
clk rising edge.
data_in[] data
Input Data input for each codeword, symbol by symbol. Valid only
when you assert the in_valid signal.
data_out data
Output Contains decoded output when the IP core asserts the
out_valid signal. The corrected symbols are in the same
order that they are entered.
eop_in
eop
Input End of packet (codeword) signal.
eop_out eop
Output End of packet (codeword) signal. This signal indicates the
packet boundaries on the data_in[] bus. When the IP
core drives this signal high, it indicates that the end of
packet is present on the data_in[] bus. The IP core
asserts this signal on the last transfer of every packet.
in_error error
Input Error signal. Specifies if the input data symbol is an error
and whether the decoder can consider it as an erasure.
Erasures-supporting decoders only.
load valid
Input Data valid signal to indicate the validity of the data signals.
When you assert the in_valid signal, the Avalon-ST data
interface signals are valid. When you deassert the
in_valid signal, the Avalon-ST data interface signals are
invalid and must be disregarded. You can assert the
in_valid signal whenever data is available. However, the
sink only captures the data from the source when the IP
core asserts the in_ready signal.
number_of_err
ors
error
Output Indicates the number of errors (decoder only). Valid when
the IP core asserts eop_out .
sop_in sop
Input Start of packet (codeword) signal.
sop_out sop
Output Start of packet (codeword) signal. This signal indicates the
codeword boundaries on the data_in[] bus. When the IP
core drives this signal high, it indicates that the start of
packet is present on the data_in[] bus. The IP core
asserts this signal on the first transfer of every codeword.
sink_ready ready
Input Data transfer ready signal to indicate that the downstream
module is ready to accept data. The source provides new
data (if available) when you assert the sink_ready signal
and stops providing new data when you deassert the
sink_ready signal. If the source is unable to provide new
data, it deasserts valid_out for one or more clock cycles
until it is prepared to drive valid data interface signals.
valid_out valid
Output
Data valid signal. The IP core asserts the valid_out signal
high, whenever a valid output is on data_out ; the IP core
deasserts the signal when there is no valid output on
data_out .
For IP cores generated within Qsys, all signals are in an Avalon-ST interface. For
encoders:
•
Input: in[0 to data width of data_in]
•
Output: out[0 to data width of data_out]
3. BCH IP Core Functional Description
683320 | 2017.11.06
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