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Table Of Contents
- BCH IP Core: User Guide
- Contents
- 1. About the BCH IP Core
- 2. BCH IP Core Getting Started
- 3. BCH IP Core Functional Description
- 4. Document Revision History
- A. BCH IP Core Document Archive
shows the number of errors the IP core detects. At the first clock cycle where the
output data is valid, sop_out is asserted high for only one cycle, indicating the start
of output packet. The IP core has forward and back pressure, which you controll with
the ready signal and sink_ready signal. Assert the sop_in and eop_in signals
correctly at the clock cycle, i.e. the first and last clock cycle of the input codeword.
3.3. BCH IP Core Parameters
Table 7. Parameters
Parameter Legal Values Default Value Description
BCH module Encoder or Decoder Encoder Specify an encoder or a decoder.
Number of bits per symbol
(m)
3 to 14 (encoder or 6 to 14
(decoder)
14 Specify the number of bits per
symbol.
Codeword length (n) parity_bits+1 : 2
m-1
8,784 Specify the codeword length. The
decoder accept a new symbol every
clock cycle if 6.5R < N. If N>=6.5R
+1, the decoder shows continuous
behavior.
Error correction capacity (t) Range derived from m. For
the decoder, the wizard caps
the range between 8 and
127.
40 Specify the number of bits to be
corrected.
Parity bits – 560 Shows the number of parity bits in the
codeword. The wizard derives this
parameter from t.
Message length (k) – 8,224 Shows the number of message bits in
the codeword. The wizard derives this
parameter from t and n.
Primitive polynomial – 17,475 Shows the primitive polynomial.
derived from the choice of m.
Parallel input data width Encoder: 1 to
min(parity_bits, k-1).
Decoder:
• d < floor(n*3/14)
• d < floor(n/
floor[2*log
2
(2*t)])
20 The number of bits to input every
clock cycle.
3.4. BCH IP Core Interfaces and Signals
Table 8. Clock and Reset Signals
Name Avalon-ST Type Direction Description
clk clk
Input The main system clock. The whole IP core operates on the
rising edge of clk .
reset reset_n
Input An active low signal that resets the entire system when
asserted. You can assert this signal asynchronously.
However, you must deassert it synchronous to the clk_clk
signal. When the IP core recovers from reset, ensure that
the data it receives is a complete packet.
3. BCH IP Core Functional Description
683320 | 2017.11.06
BCH IP Core: User Guide
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