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Contents
1. About the BCH IP Core.................................................................................................... 3
1.1. Intel
®
DSP IP Core Features....................................................................................3
1.2. BCH IP Core Features.............................................................................................3
1.3. DSP IP Core Device Family Support..........................................................................4
1.4. BCH IP Core Release Information.............................................................................4
1.5. DSP IP Core Verification..........................................................................................5
1.6. BCH IP Core Performance and Resource Utilization..................................................... 5
2. BCH IP Core Getting Started........................................................................................... 8
2.1. Installing and Licensing Intel FPGA IP Cores.............................................................. 8
2.1.1. Intel FPGA IP Evaluation Mode.....................................................................8
2.1.2. BCH IP Core Intel FPGA IP Evaluation Mode Timeout Behavior........................11
2.2. IP Catalog and Parameter Editor............................................................................ 11
2.3. Generating IP Cores (Intel Quartus Prime Pro Edition)...............................................13
2.3.1. IP Core Generation Output (Intel Quartus Prime Pro Edition)..........................14
2.4. Simulating Intel FPGA IP Cores.............................................................................. 17
2.5. DSP Builder for Intel FPGAs Design Flow................................................................. 17
3. BCH IP Core Functional Description.............................................................................. 18
3.1. BCH IP Core Encoder............................................................................................18
3.2. BCH IP Core Decoder............................................................................................19
3.3. BCH IP Core Parameters....................................................................................... 20
3.4. BCH IP Core Interfaces and Signals........................................................................ 20
3.4.1. Avalon-ST Interfaces in DSP IP Cores......................................................... 22
4. Document Revision History........................................................................................... 23
A. BCH IP Core Document Archive.....................................................................................24
Contents
BCH IP Core: User Guide
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