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3. BCH IP Core Functional Description
This topic describes the IP core’s architecture, interfaces, and signals.
You can parameterize the BCH IP core as an encoder or a decoder. The encoder
receives data packets and generates the check symbols; the decoder detects and
corrects errors.
3.1. BCH IP Core Encoder
The BCH encoder has a parallel architecture with an input and output of d data bits.
When the encoder receives data symbols, it generates check symbols for a given
codeword and sends the input codeword with the check symbols to the output
interface. The encoder uses backpressure on the upstream component when it
generates the check symbols.
Figure 7. Encoder Timing
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 236 237 238 239 1 2 3 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 234235 236 237 238
239
1 114 61 30 244
75
1 2
clk
reset
load
sop_in
eop_in
data_in[7:0]
ready
valid_out
sop_out
eop_out
data_out[7:0]
sink_ready
The ready signal indicates that the encoder can accept incoming stream. On the clk
rising edge, if the encoder ready signal is high, send input data stream via data_in
port and assert load high to indicate valid input data. Assume the full message word
needs X clock signals. When this input process reaches X-1 clock cycles, the encoder
ready signal goes low. At the next clk rising edge, the encoder accepts the input
from data_in port, and the encoder receives the full message word. Before the
ready signal returns to high again, the encoder does not accept new input data.
When valid_outt signal is asserted high, output encoded codeword is valid at the
data_out port. At the first clock cycle where the output data is valid, sop_out is
asserted high for only one cycle, indicating the start of packet. The IP core has
forward and back pressure, which you can control with the ready and sink_ready
signal. Assert the sop_in and eop_in signals correctly at the clock cycle, i.e. the first
and last clock cycle of the input codeword.
683320 | 2017.11.06
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