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2.4. Simulating Intel FPGA IP Cores
The Intel Quartus Prime software supports IP core RTL simulation in specific EDA
simulators. IP generation creates simulation files, including the functional simulation
model, any testbench (or example design), and vendor-specific simulator setup scripts
for each IP core. Use the functional simulation model and any testbench or example
design for simulation. IP generation output may also include scripts to compile and run
any testbench. The scripts list all models or libraries you require to simulate your IP
core.
The Intel Quartus Prime software provides integration with many simulators and
supports multiple simulation flows, including your own scripted and custom simulation
flows. Whichever flow you choose, IP core simulation involves the following steps:
1. Generate simulation model, testbench (or example design), and simulator setup
script files.
2. Set up your simulator environment and any simulation scripts.
3. Compile simulation model libraries.
4. Run your simulator.
2.5. DSP Builder for Intel FPGAs Design Flow
DSP Builder for Intel FPGAs shortens digital signal processing (DSP) design cycles by
helping you create the hardware representation of a DSP design in an algorithm-
friendly development environment.
This IP core supports DSP Builder for Intel FPGAs. Use the DSP Builder for Intel FPGAs
flow if you want to create a DSP Builder for Intel FPGAs model that includes an IP core
variation; use IP Catalog if you want to create an IP core variation that you can
instantiate manually in your design.
Related Information
Using MegaCore Functions chapter in the DSP Builder for Intel FPGAs Handbook.
2. BCH IP Core Getting Started
683320 | 2017.11.06
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BCH IP Core: User Guide
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