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File Name Description
<your_ip>.qgsimc (Platform Designer
systems only)
Simulation caching file that compares the .qsys and .ip files with the current
parameterization of the Platform Designer system and IP core. This comparison
determines if Platform Designer can skip regeneration of the HDL.
<your_ip>.qgsynth (Platform
Designer systems only)
Synthesis caching file that compares the .qsys and .ip files with the current
parameterization of the Platform Designer system and IP core. This comparison
determines if Platform Designer can skip regeneration of the HDL.
<your_ip>.qip
Contains all information to integrate and compile the IP component.
<your_ip>.csv
Contains information about the upgrade status of the IP component.
<your_ip>.bsf
A symbol representation of the IP variation for use in Block Diagram Files
(.bdf).
<your_ip>.spd Input file that ip-make-simscript requires to generate simulation scripts.
The .spd file contains a list of files you generate for simulation, along with
information about memories that you initialize.
<your_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP
components you create for use with the Pin Planner.
<your_ip>_bb.v Use the Verilog blackbox (_bb.v) file as an empty module declaration for use
as a blackbox.
<your_ip>_inst.v or _inst.vhd
HDL example instantiation template. Copy and paste the contents of this file
into your HDL file to instantiate the IP variation.
<your_ip>.regmap
If the IP contains register information, the Intel Quartus Prime software
generates the .regmap file. The .regmap file describes the register map
information of master and slave interfaces. This file complements
the .sopcinfo file by providing more detailed register information about the
system. This file enables register display views and user customizable statistics
in System Console.
<your_ip>.svd
Allows HPS System Debug tools to view the register maps of peripherals that
connect to HPS within a Platform Designer system.
During synthesis, the Intel Quartus Prime software stores the .svd files for
slave interface visible to the System Console masters in the .sof file in the
debug session. System Console reads this section, which Platform Designer
queries for register map information. For system slaves, Platform Designer
accesses the registers by name.
<your_ip>.v <your_ip>.vhd
HDL files that instantiate each submodule or child IP core for synthesis or
simulation.
mentor/ Contains a msim_setup.tcl script to set up and run a ModelSim simulation.
aldec/ Contains a Riviera*-PRO script rivierapro_setup.tcl to setup and run a
simulation.
/synopsys/vcs
/synopsys/vcsmx
Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.
Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to
set up and run a VCS MX* simulation.
/cadence Contains a shell script ncsim_setup.sh and other setup files to set up and
run an NCSIM simulation.
/submodules
Contains HDL files for the IP core submodule.
<IP submodule>/ Platform Designer generates /synth and /sim sub-directories for each IP
submodule directory that Platform Designer generates.
2. BCH IP Core Getting Started
683320 | 2017.11.06
BCH IP Core: User Guide
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