BCH IP Core User Guide Updated for Intel® Quartus® Prime Design Suite: 17.1 ID: 683320 Online Version Send Feedback UG-BCH Version: 2017.11.
Contents Contents 1. About the BCH IP Core.................................................................................................... 3 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. Intel® DSP IP Core Features....................................................................................3 BCH IP Core Features.............................................................................................3 DSP IP Core Device Family Support..........................................................................
683320 | 2017.11.06 Send Feedback 1. About the BCH IP Core Related Information • BCH IP Core Document Archive on page 24 Provides a list of user guides for previous versions of the BCH IP Core IP core. • Introduction to Intel FPGA IP Cores Provides general information about all Intel FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.
1. About the BCH IP Core 683320 | 2017.11.06 1.3. DSP IP Core Device Family Support Intel offers the following device support levels for Intel FPGA IP cores: Table 1. • Advance support—the IP core is available for simulation and compilation for this device family. FPGA programming file (.pof) support is not available for Quartus Prime Pro Stratix 10 Edition Beta software and as such IP timing closure cannot be guaranteed.
1. About the BCH IP Core 683320 | 2017.11.06 Table 2. Release Information Item Description Version 17.1 Release Date Novermber 2017 Ordering Code IP-BCH (IPR-BCH) Intel verifies that the current version of the Quartus Prime software compiles the previous version of each IP core. Intel does not verify that the Quartus Prime software compiles IP core versions older than the previous version. The Intel FPGA IP Release Notes lists any exceptions.
1. About the BCH IP Core 683320 | 2017.11.
1. About the BCH IP Core 683320 | 2017.11.
683320 | 2017.11.06 Send Feedback 2. BCH IP Core Getting Started 2.1. Installing and Licensing Intel FPGA IP Cores The Intel Quartus® Prime software installation includes the Intel FPGA IP library. This library provides many useful IP cores for your production use without the need for an additional license. Some Intel FPGA IP cores require purchase of a separate license for production use.
2. BCH IP Core Getting Started 683320 | 2017.11.06 Intel FPGA IP Evaluation Mode supports the following operation modes: • Tethered—Allows running the design containing the licensed Intel FPGA IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial joint test action group (JTAG) cable connected between the JTAG port on your board and the host computer, which is running the Intel Quartus Prime Programmer for the duration of the hardware evaluation period.
2. BCH IP Core Getting Started 683320 | 2017.11.06 Figure 2.
2. BCH IP Core Getting Started 683320 | 2017.11.06 Related Information • Intel Quartus Prime Licensing Site • Intel FPGA Software Installation and Licensing 2.1.2. BCH IP Core Intel FPGA IP Evaluation Mode Timeout Behavior All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If a design has more than one IP core, the time-out behavior of the other IP cores may mask the time-out behavior of a specific IP core .
2. BCH IP Core Getting Started 683320 | 2017.11.06 Figure 3. IP Parameter Editor (Intel Quartus Prime Pro Edition) IP Parameters Figure 4.
2. BCH IP Core Getting Started 683320 | 2017.11.06 2.3. Generating IP Cores (Intel Quartus Prime Pro Edition) Quickly configure Intel FPGA IP cores in the Intel Quartus Prime parameter editor. Double-click any component in the IP Catalog to launch the parameter editor. The parameter editor allows you to define a custom variation of the IP core. The parameter editor generates the IP variation synthesis and optional simulation files, and adds the .
2. BCH IP Core Getting Started 683320 | 2017.11.06 Note: Refer to your IP core user guide for information about specific IP core parameters. 5. Click Generate HDL. The Generation dialog box appears. 6. Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications. 7. To generate a simulation testbench, click Generate ➤ Generate Testbench System. Specify testbench generation options, and then click Generate. 8.
2. BCH IP Core Getting Started 683320 | 2017.11.06 Figure 6. Individual IP Core Generation Output (Intel Quartus Prime Pro Edition) .ip - Top-level IP variation file - IP core variation files .bsf - Block symbol schematic file .cmp - VHDL component declaration .ppf - XML I/O pin information file .qip - Lists files for IP core synthesis .spd - Simulation startup scripts _bb.
2. BCH IP Core Getting Started 683320 | 2017.11.06 File Name Description .qgsimc (Platform Designer Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. .qgsynth (Platform Designer systems only) Synthesis caching file that compares the .qsys and .
2. BCH IP Core Getting Started 683320 | 2017.11.06 2.4. Simulating Intel FPGA IP Cores The Intel Quartus Prime software supports IP core RTL simulation in specific EDA simulators. IP generation creates simulation files, including the functional simulation model, any testbench (or example design), and vendor-specific simulator setup scripts for each IP core. Use the functional simulation model and any testbench or example design for simulation.
683320 | 2017.11.06 Send Feedback 3. BCH IP Core Functional Description This topic describes the IP core’s architecture, interfaces, and signals. You can parameterize the BCH IP core as an encoder or a decoder. The encoder receives data packets and generates the check symbols; the decoder detects and corrects errors. 3.1. BCH IP Core Encoder The BCH encoder has a parallel architecture with an input and output of d data bits.
3. BCH IP Core Functional Description 683320 | 2017.11.06 Shortened Codewords The BCH IP core supports shortened codewords. A shortened codeword contains fewer symbols than the maximum value of N, which is 2M –1, where N is the total number of symbols per codeword and M is the number of bits per symbol. A shortened codeword is mathematically equivalent to a maximum-length code with the extra data symbols at the start of the codeword set to 0. For example, (220,136) is a shortened codeword of (255,171).
3. BCH IP Core Functional Description 683320 | 2017.11.06 shows the number of errors the IP core detects. At the first clock cycle where the output data is valid, sop_out is asserted high for only one cycle, indicating the start of output packet. The IP core has forward and back pressure, which you controll with the ready signal and sink_ready signal. Assert the sop_in and eop_in signals correctly at the clock cycle, i.e. the first and last clock cycle of the input codeword. 3.3.
3. BCH IP Core Functional Description 683320 | 2017.11.06 Table 9. Avalon-ST Input and Output Interface Signals Name Avalon-ST Type Direction Description ready ready Output Data transfer ready signal to indicate that the sink is ready to accept data. The sink interface drives the ready signal to control the flow of data across the interface. The sink interface captures the data interface signals on the current clk rising edge.
3. BCH IP Core Functional Description 683320 | 2017.11.06 For decoders: • Input: in[0 to data width of data_in] • Output: out [0 to data width+number_errors | data_out] 3.4.1. Avalon-ST Interfaces in DSP IP Cores Avalon-ST interfaces define a standard, flexible, and modular protocol for data transfers from a source interface to a sink interface. The input interface is an Avalon-ST sink and the output interface is an Avalon-ST source.
683320 | 2017.11.06 Send Feedback 4. Document Revision History BCH IP Core User Guide revision history. Date Version Changes 2017.11.06 17.1 • • Added support for Intel Cyclone 10 devices Corrected signal names in encoder and decoder descriptions. 2017.02.14 16.1 • • Removed product ID and vendor ID. Corrected Error correction capability (t) max value to 127 2015.10.01 15.1 Added product ID and ordering code. 2015.05.01 15.0 Initial release Intel Corporation. All rights reserved.
683320 | 2017.11.06 Send Feedback A. BCH IP Core Document Archive If the table does not list an IP core version, the user guide for the previous IP core version applies. IP Core Version User Guide 16.1 BCH IP Core User Guide 15.1 BCH IP Core User Guide Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.
