Datasheet

Processor Configuration Registers
92 Datasheet, Volume 2
2.8.34 C1PWLRCTRL—Channel 1 Partial Write Line Read Control
Register
This register is to configure the DRAM controller's partial write policies.
2.8.35 C1ODTCTRL—Channel 1 ODT Control Register
This register provides ODT controls.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 665–666h
Reset Value: 0000h
Access: RW, RO
Bit Attr
Reset
Value
Description
15:14 RO 00b Reserved
13:8 RW 000000b
Read And Merging-write Window (C1sd_cr_rdmodwr_window)
This configuration setting defines the time period (in mclks) between the
read and the merging-write commands on the DRAM bus. This window
duration is a function of the tRD and write data latency through the chipset.
7:5 RO 000b Reserved
4:0 RW 00000b
Partial Write Trip Threshold (PWTRIP)
This configuration setting indicates the threshold for number of partial writes
which are blocked from arbitration before indicating a trip.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 69C–69Fh
Reset Value: 0000_0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
31:12 RO 00000h Reserved
11:8 RW 0h
DRAM ODT for Read Commands (sd1_cr_odt_duration_rd)
This field specifies the duration in DRAM bus clocks to assert DRAM ODT for
Read Commands. The Async value should be used when the Dynamic
Powerdown bit is set. Otherwise, use the Sync value.
7:4 RW 0h
DRAM ODT for Write Commands (sd1_cr_odt_duration_wr)
This field specifies the duration in DRAM bus clocks to assert DRAM ODT for
Write Commands. The Async value should be used when the Dynamic
Powerdown bit is set. Otherwise, use the Sync value.
3:0 RW 0h
MCH ODT for Read Commands (sd1_cr_mchodt_duration)
This field specifies the duration in DRAM bus clocks to assert MCH ODT for
Read Commands.