Datasheet
Datasheet, Volume 2 89
Processor Configuration Registers
2.8.30 C1CYCTRKACT—Channel 1 CYCTRK ACT Register
This register provides Channel 1 CYCTRK ACT control.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 652–655h
Reset Value: 0000_0000h
Access: RW, RO
Bit Attr
Reset
Value
Description
31:30 RO 0h Reserved
29 RW 0b
FAW Windowcnt Bug Fix Disable (FAWWBFD)
This bit disables the CYCTRK FAW windowcnt bug fix.
1 = Disable CYCTRK FAW windowcnt bug fix
0 = Enable CYCTRK FAW windowcnt bug fix
(C1sd_cr_cyctrk_faw_windowcnt_fix_disable)
28 RW 0b
FAW Phase Bug Fix Disable (FAWPBFD)
This bit disables the CYCTRK FAW phase indicator bug fix.
1 = Disable CYCTRK FAW phase indicator bug fix
0 = Enable CYCTRK FAW phase indicator bug fix
(C1sd_cr_cyctrk_faw_phase_fix_disable)
27:22 RW 000000b
ACT Window Count (C1sd_cr_act_windowcnt)
This field indicates the window duration (in DRAM clocks) during which the
controller counts the number of activate commands which are launched to a
particular rank. If the number of activate commands launched within this
window is greater than 4, then a check is implemented to block launch of
further activates to this rank for the rest of the duration of this window.
21 RW 0b
Max ACT Check (C1sd_cr_maxact_dischk)
This bit enables the check which ensures that there are no more than four
activates to a particular rank in a given window.
20:17 RW 0000b
ACT to ACT Delayed (C1sd_cr_act_act)
This field indicates the minimum allowed spacing (in DRAM clocks) between
two ACT commands to the same rank.
This field corresponds to tRRD in the DDR specification.
16:13 RW 0000b
PRE to ACT Delayed (C1sd_cr_pre_act)
This field indicates the minimum allowed spacing (in DRAM clocks) between
the PRE and ACT commands to the same rank-bank:12:9R/W0000bPRE-ALL
to ACT Delayed (C1sd_cr_preall_act):This field indicates the minimum
allowed spacing (in DRAM clocks) between the PRE-ALL and ACT commands
to the same rank. This field corresponds to tRP in the DDR specification.
12:9 RW 0h
ALLPRE to ACT Delay (C1sd_cr_preall_act)
From the launch of a prechargeall command wait for these many numbers of
mclks before launching a activate command. Corresponds to tPALL_RP.
8:0 RW
00000000
0b
REF to ACT Delayed (C1sd_cr_rfsh_act)
This field indicates the minimum allowed spacing (in DRAM clocks) between
REF and ACT commands to the same rank. This field corresponds to tRFC in
the DDR specification.