Datasheet

Datasheet, Volume 2 83
Processor Configuration Registers
9RW 0b
DODTRD0R1 (sd0_cr_rdrank0_r1odt)
Assert rank1 ODT during Reads from RANK0.
1 = ON
0 = OFF
8RW 0b
DODTRD0R0 (sd0_cr_rdrank0_r0odt)
Assert rank0 ODT during Reads from RANK0.
1 = ON
0 = OFF
7RW 0b
DODTWR1R3 (sd0_cr_wrrank1_r3odt)
Assert rank3 ODT during Writes to RANK1.
1 = ON
0 = OFF
6RW 0b
DODTWR1R2 (sd0_cr_wrrank1_r2odt)
Assert rank2 ODT during Writes to RANK1.
1 = ON
0 = OFF
5RW 0b
DODTWR1R1 (sd0_cr_wrrank1_r1odt)
Assert rank1 ODT during Writes to RANK1.
1 = ON
0 = OFF
4RW 0b
DODTWR1R0 (sd0_cr_wrrank1_r0odt)
Assert rank0 ODT during Writes to RANK1.
1 = ON
0 = OFF
3RW 0b
DODTWR0R3 (sd0_cr_wrrank0_r3odt)
Assert rank3 ODT during Writes to RANK0.
1 = ON
0 = OFF
2RW 0b
DODTWR0R2 (sd0_cr_wrrank0_r2odt)
Assert rank2 ODT during Writes to RANK0.
1 = ON
0 = OFF
1RW 0b
DODTWR0R1 (sd0_cr_wrrank0_r1odt)
Assert rank1 ODT during Writes to RANK0.
1 = ON
0RW 0b
DODTWR0R0 (sd0_cr_wrrank0_r0odt)
Assert rank0 ODT during Writes to RANK0.
1 = ON
0 = OFF
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 298–29Bh
Reset Value: 0000_0000h
Access: RW, RO
Bit Attr
Reset
Value
Description