Datasheet

Datasheet, Volume 2 81
Processor Configuration Registers
2.8.17 C0JEDEC—Channel 0 JEDEC Control Register
This is the Channel 0 JEDEC Control Register.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 271h
Reset Value: 00h
Access: RW, RO
Bit Attr
Reset
Value
Description
7RW 0b
Functional Loopback Mode Enable (FLME)
This configuration setting indicates that the chip is placed in FME (Functional
Loopback Mode Enable) mode.
6RW 0b
Write Levelization Mode (WRLVLMDE)
This configuration bit indicates that memory controller is in write levelization
mode.
5:4 RW 00b
EMRS Mode (sd0_cr_emrs_mode)
This configuration field indicates the type of the EMRS command being issued
as a part of the JEDEC initialization.
00 = no EMRS command
01 = EMRS
10 = EMRS2
11 = EMRS3
3:1 RW 000b
Mode Select (sd0_cr_sms)
This configuration setting indicates the mode in which the controller is
operating.
000 = Post Reset state
001 = NOP Command Enable
010 = All Banks Pre-charge Enable
011 = Mode Register Set Enable
100 = Extended Mode Register Set Enable
101 = Reserved
110 = CBR Refresh Enable
111 = Normal mode of operation.
0RO 0bReserved