Datasheet

Processor Configuration Registers
80 Datasheet, Volume 2
21:20 RW 00b
DRAM Refresh Hysterisis (REFHYSTERISIS)
Hysterisis level — useful for dref_high watermark cases. The dref_high flag is
set when the dref_high watermark level is exceeded, and is cleared when the
refresh count is less than the hysterisis level. This bit should be set to a value
less than the high watermark level.
00 = 3
01 = 4
10 = 5
11 = 6
19:18 RW 00b
DRAM Refresh Panic Watermark (REFPANICWM)
When the refresh count exceeds this level, a refresh request is launched to
the scheduler and the dref_panic flag is set.
00 = 5
01 = 6
10 = 7
11 = 8
17:16 RW 00b
DRAM Refresh High Watermark (REFHIGHWM)
When the refresh count exceeds this level, a refresh request is launched to
the scheduler and the dref_high flag is set.
00 = 3
01 = 4
10 = 5
11 = 6
15:14 RW 00b
DRAM Refresh Low Watermark (REFLOWWM)
When the refresh count exceeds this level, a refresh request is launched to
the scheduler and the dref_low flag is set.
00 = 1
01 = 2
10 = 3
11 = 4
13:0 RW 0C30h
Refresh Counter Time Out Value (REFTIMEOUT)
Program this field with a value that will provide 7.8 us at mb4clk frequency.
At various mb4clk frequencies this results in the following values:
266 MHz -> 820 hex
333 MHz -> A28 hex
400 MHz -> C30 hex
533 MHz -> 1040 hex
666 MHz -> 1450 hex
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 269–26Eh
Reset Value: 241830000C30h
Access: RW, RO
Bit Attr
Reset
Value
Description