Datasheet

Processor Configuration Registers
78 Datasheet, Volume 2
2.8.14 C0CYCTRKREFR—Channel 0 CYCTRK REFR Register
This register provides Channel 0 CYCTRK Refresh control.
2.8.15 C0PWLRCTRL—Channel 0 Partial Write Line Read Control
Register
This register configures the DRAM controller partial write policies.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 25B–25Ch
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
15:13 RO 000b Reserved
12:9 RW 0h
Same Rank Precharge All to Refresh Delay (C0sd_cr_pchgall_rfsh)
This field indicates the minimum allowed spacing (in DRAM clocks) between
the PRE-ALL and REF commands to the same rank.
8:0 RW 000h
Same Rank Refresh to Refresh Delay (C0sd_cr_rfsh_rfsh)
This field indicates the minimum allowed spacing (in DRAM clocks) between
two REF commands to the same rank.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 265–266h
Reset Value: 0000h
Access: RW, RO
Bit Attr
Reset
Value
Description
15:14 RO 00b Reserved
13:8 RW 00h
Read And Merging-write Window (C0sd_cr_rdmodwr_window)
This configuration setting defines the time period (in mclks) between the
read and the merging-write commands on the DRAM bus. This window
duration is a function of the tRD and write data latency through the chipset.
7:5 RO 000b Reserved
4:0 RW 00h
Partial Write Trip Threshold (PWTRIP)
This configuration setting indicates the threshold for number of partial writes
which are blocked from arbitration before indicating a trip.